Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
70
AT90S/LS4433
1042G–AVR–09/02
Scanning Multiple
Channels
Since change of analog channel always is delayed until a conversion is finished, the
Free Run mode can be used to scan multiple channels without interrupting the con-
verter. Typically, the ADC Conversion Complete interrupt will be used to perform the
channel shift. However, the user should take the following fact into consideration: The
interrupt triggers once the result is ready to be read. In Free Run mode, the next conver-
sion will start immediately when the interrupt triggers. If ADMUX is changed after the
interrupt triggers, the next conversion has already started and the old setting is used.
ADC Noise Canceling
Techniques
Digital circuitry inside and outside the AT90S4433 generates EMI, which might affect
the accuracy of analog measurements. If conversion accuracy is critical, the noise level
can be reduced by applying the following techniques:
1. The analog part of the AT90S4433 and all analog components in the application
should have a separate analog ground plane on the PCB. This ground plane is
connected to the digital ground plane via a single point on the PCB.
2. Keep analog signal paths as short as possible. Make sure analog tracks run over
the analog ground plane and keep them well away from high-speed switching
digital tracks.
3. The AVCC pin on the AT90S4433 should be connected to the digital V
CC
supply
voltage via an LC network as shown in Figure 49.
4. Use the ADC Noise Canceler function to reduce induced noise from the CPU.
5. If some Port C pins are used as digital outputs, it is essential that these do not
switchwhileaconversionisinprogress.
Figure 49. ADC Power Connections
Note that since AVCC feeds the Port C output drivers, the RC network shown should not
be employed if any Port C serve as outputs.
28
27
26
25
24
23
22
21
20
19
PC5 (ADC5)
PC4 (ADC4)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
AGND
AREF
AVCC
PB5
VCC
100 nF
Analog Ground Plane
AT90S4433
10 µH