Manual

7
AT90S/LS4433
1042G–AVR–09/02
Architectural
Overview
The fast-access Register File concept contains 32 x 8-bit general purpose working reg-
isters with a single clock cycle access time. This means that during one single clock
cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output
from the Register File, the operation is executed, and the result is stored back in the
Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing, enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the constant table look-up func-
tion. These added function registers are the 16-bit X-, Y-, and Z-register.
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 5
shows the AT90S4433 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional Memory Addressing modes can be
used on the Register File as well. This is enabled by the fact that the Register File is
assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be
accessed as though they were ordinary memory locations.
Figure 5. The AT90S4433 AVR RISC Architecture
2K X 16
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
Interrupt
Unit
SPI
Unit
8-bit
Timer/Counter
Watchdog
Timer
Analog to Digital
Converter
Analog
Comparator
20
I/O Lines
256 x 8
EEPROM
Data Bus 8-bit
Serial
UART
16-bit
Timer/Counter
with PWM
128 x 8
Data
SRAM
Direct Addressing
Indirect Addressing