Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
67
AT90S/LS4433
1042G–AVR–09/02
Figure 47. ADC Timing Diagram, Single Conversion
Figure 48. ADC Timing Diagram, Free Run Conversion
ADC Noise Canceler
Function
The ADC features a Noise Canceler that enables conversion during Idle mode to reduce
noise induced from the CPU core. To make use of this feature, the following procedure
should be used:
1. Make sure that the ADC is enabled and is not busy converting. Single Conver-
sion mode must be selected and the ADC conversion complete interrupt must be
enabled. Thus:
ADEN = 1
ADSC = 0
ADFR = 0
ADIE = 1
2. Enter Idle mode. The ADC will start a conversion once the CPU has been halted.
3. If no other interrupts occur before the ADC conversion completes, the ADC inter-
rupt will wake up the MCU and execute the ADC conversion complete interrupt
routine.
1
2 3 4 5 6 7 8
9
10 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
complete
MUX and REFS
Update
11 12 13
MSB of Result
LSB of Result
ADC Clock
ADSC
Hold Strobe
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next
Conversion