Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
66
AT90S/LS4433
1042G–AVR–09/02
keeps running for as long as the ADEN bit is set and is continuously reset when ADEN
is low.
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at
the following rising edge of the ADC clock cycle. The actual sample-and-hold takes
place 1.5 ADC clock cycles after the start of the conversion. The result is ready and writ-
ten to the ADC Result Register after 13 cycles. In Single Conversion mode, the ADC
needs one more clock cycle before a new conversion can be started (see Figure 47). If
ADSC is set high in this period, the ADC will start the new conversion immediately. In
Free Run mode, a new conversion will be started immediately after the result is written
to the ADC Result Register. Using Free Run mode and an ADC clock frequency of 200
kHz gives the lowest conversion time, 65 µs, equivalent to 15.4 kSPS. For a summary of
conversion times, see Table 21.
Figure 46. ADC Timing Diagram, First Conversion (Single Conversion Mode)
MSB of Result
LSB of Result
ADC Clock
ADSC
Hold Strobe
ADIF
ADCH
ADCL
Cycle Number
ADEN
1 212
13
14 15
16 17
18
19 20 21 22 23
24 25 26 1
2
Dummy Conversion Actual Conversion
Second
Conversion
Table 21. ADC Conversion Time
Condition
Sample Cycle
Number
Result
Ready(Cycle Number)
Total Conversion
Time (Cycles)
Total Conversion
Time (µs)
1st Conversion, Free Run 13.5 25 25 125 - 500
1st Conversion, Single 13.5 25 26 130 - 520
Free Run Conversion 1.5 13 13 65 - 260
Single Conversion 1.5 13 14 70 - 280