Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
64
AT90S/LS4433
1042G–AVR–09/02
Analog-to-Digital
Converter
Features • 10-bit Resolution
• ±2 LSB Absolute Accuracy
• 0.5 LSB Integral Non-linearity
• 65 - 260 µs Conversion Time
• Up to 15 kSPS
• Six Multiplexed Input Channels
• Rail-to-Rail Input Range
• Free Run or Single Conversion Mode
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
The AT90S4433 features a 10-bit successive approximation ADC. The ADC is con-
nected to a 6-channel Analog Multiplexer, which allows each pin of Port C to be used as
an input for the ADC. The ADC contains a Sample and Hold Amplifier, which ensures
that the input voltage to the ADC is held at a constant level during conversion. A block
diagram of the ADC is shown in Figure 44.
The ADC has two separate analog supply voltage pins: AVCC and AGND. AGND must
be connected to GND, and the voltage on AVCC must not differ from V
CC
more than
±0.3V. See the section “ADC Noise Canceling Techniques” on page 70 for how to con-
nect these pins.
An external reference voltage must be applied to the AREF pin. This voltage must be in
the range 2.0 - AVCC.
Figure 44. Analog-to-Digital Converter Block Schematic
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
90
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL & STATUS
REGISTER (ADCSR)
ADC DATA REGISTER
(ADCH/ADCL)
MUX2
ADIE
ADIE
ADFR
ADSC
ADEN
ADIF
ADIF
MUX1
MUX0
ADPS0
ADPS1
ADPS2
6-
CHANNEL
MUX
CONVERSION LOGIC10-BIT DAC
+
-
SAMPLE & HOLD
COMPARATOR
Analog
Inputs
External
Reference
Voltage