Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
 
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
 
- Sleep Modes
 
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents

59
AT90S/LS4433
1042G–AVR–09/02
• Bit 3 – TXEN: Transmitter Enable
This bit enables the UART Transmitter when set (one). When disabling the Transmitter
while transmitting a character, the Transmitter is not disabled before the character in the
Shift Register plus any following character in UDR has been completely transmitted.
• Bit 2 – CHR9: 9-bit Characters
When this bit is set (one), transmitted and received characters are nine bits long, plus
start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in
UCSRB, respectively. The ninth data bit can be used as an extra stop bit or a parity bit.
• Bit 1 – RXB8: Receive Data Bit 8
When CHR9 is set (one), RXB8 is the ninth data bit of the received character.
• Bit 0 – TXB8:TransmitDataBit8
When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted.
Baud Rate Generator The Baud Rate Generator is a frequency divider, which generates baud rates according
to the following equation:
• BAUD = Baud Rate
• f
CK
= Crystal Clock frequency
• UBR = Contents of the UBRRHI and UBRR Registers, (0 - 4095)
For standard crystal frequencies, the most commonly used baud rates can be generated
by using the UBR settings in Table 19. UBR values that yield an actual baud rate differ-
ing less than 2% from the target baud rate are boldface in the table. However, using
baud rates that have more than 1% error is not recommended. High error ratings give
less noise resistance.
BAUD
f
CK
16(UBR 1 )+
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