Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
57
AT90S/LS4433
1042G–AVR–09/02
UART Control
UART I/O Data Register – UDR
The UDR Register is actually two physically separate registers sharing the same I/O
address. When writing to the register, the UART Transmit Data Register is written.
When reading from UDR, the UART Receive Data Register is read.
UART Control and Status
Register A – UCSRA
• Bit 7 – RXC: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift
Register to UDR. The bit is set regardless of any detected framing errors. When the
RXCIE bit in UCSRB is set, the UART Receive Complete interrupt will be executed
when RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data
reception is used, the UART Receive Complete Interrupt routine must read UDR in
order to clear RXC, otherwise a new interrupt will occur once the interrupt routine
terminates.
• Bit 6 – TXC: UART Transmit Complete
This bit is set (one) when the entire character (including the stop bit) in the Transmit
Shift Register has been shifted out and no new data has been written to UDR. This flag
is especially useful in half-duplex communications interfaces, where a transmitting appli-
cation must enter Receive mode and free the communications bus immediately after
completing the transmission.
When the TXCIE bit in UCSRB is set, setting of TXC causes the UART Transmit Com-
plete interrupt to be executed. TXC is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by
writing a logical “1” to the bit.
• Bit 5 – UDRE: UART Data Register Empty
This bit is set (one) when a character written to UDR is transferred to the Transmit Shift
Register. Setting of this bit indicates that the Transmitter is ready to receive a new char-
acter for transmission.
When the UDRIE bit in UCSRB is set, the UART Transmit Complete interrupt to be exe-
cuted as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven
data transmittal is used, the UART Data Register Empty Interrupt routine must write
UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt rou-
tine terminates.
UDRE is set (one) during reset to indicate that the transmitter is ready.
Bit 76543210
$0C ($2C) MSB LSB UDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
InitialValue00000000
Bit 76543210
$0B ($2B) RXC TXC UDRE FE OR ––MPCM UCSRA
Read/Write R R/W RRRRRR/W
InitialValue00100000