Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
53
AT90S/LS4433
1042G–AVR–09/02
UART The AT90S4433 features a full duplex (separate Receive and Transmit Registers) Uni-
versal Asynchronous Receiver and Transmitter (UART). The main features are:
•
Baud Rate Generator Generates any Baud Rate
• High Baud Rates at Low XTAL Frequencies
• 8 or 9 Bits Data
• Noise Filtering
• Overrun Detection
• Framing Error Detection
• False Start Bit Detection
• Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete
• Multi-processor Communication Mode
Data Transmission A block schematic of the UART Transmitter is shown in Figure 40.
Figure 40. UART Transmitter
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data
Register (UDR). Data is transferred from UDR to the Transmit Shift Register when:
• A new character has been written to UDR after the stop bit from the previous
character has been shifted out. The Shift Register is loaded immediately.
• A new character has been written to UDR before the stop bit from the previous
character has been shifted out. The Shift Register is loaded when the stop bit of the
character currently being transmitted has been shifted out.
When data is transferred from UDR to the Shift Register, the UDRE (UART Data Regis-
ter Empty) bit in the UART Control and Status Register A, UCSRA, is set. When this bit
is set (one), the UART is ready to receive the next character. At the same time as the
UART CONTROL
AND STAUS
REGISTER B (UCSRB)
UART CONTROL
AND STAUS
REGISTER A (UCSRA)