Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
39
AT90S/LS4433
1042G–AVR–09/02
• Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1, and 0
The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer/Counter1.
The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes
are scaled directly from the CK Oscillator clock. If the external pin modes are used for
Timer/Counter0, transitions on PD5/(T1) will clock the counter even if the pin is config-
ured as an output. This feature can give the user software control of the counting.
Timer/Counter1 – TCNT1H and
TCNT1L
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To
ensure that both the High and Low Bytes are read and written simultaneously when the
CPU accesses these registers, the access is performed using an 8-bit temporary regis-
ter (TEMP). This temporary register is also used when accessing OCR1 and ICR1. If the
main program and interrupt routines perform access to registers using TEMP, interrupts
must be disabled during access from the main program (and from interrupt routines if
interrupts are allowed from within interrupt routines).
• TCNT1 Timer/Counter1 Write
When the CPU writes to the High Byte TCNT1H, the written data is placed in the TEMP
Register. Next, when the CPU writes the Low Byte TCNT1L, this byte of data is com-
bined with the byte data in the TEMP Register, and all 16 bits are written to the TCNT1
Timer/Counter1 Register simultaneously. Consequently, the High Byte TCNT1H must
be accessed first for a full 16-bit register write operation.
• TCNT1 Timer/Counter1 Read
When the CPU reads the Low Byte TCNT1L, the data of the Low Byte TCNT1L is sent
to the CPU and the data of the High Byte TCNT1H is placed in the TEMP Register.
When the CPU reads the data in the High Byte TCNT1H, the CPU receives the data in
Table 12. Clock 1 Prescale Select
CS12 CS11 CS10 Description
0 0 0 Stop, the Timer/Counter1 is stopped.
001CK
010CK/8
011CK/64
100CK/256
1 0 1 CK/1024
1 1 0 External Pin T1, falling edge
1 1 1 External Pin T1, rising edge
Bit 151413121110 9 8
$2D ($4D) MSB TCNT1H
$2C ($4C) LSB TCNT1L
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
InitialValue00000000
00000000