Manual

28
AT90S/LS4433
1042G–AVR–09/02
• Bit 6 – INTF0: External Interrupt Flag0
When an edge on the INT0 pin triggers an interrupt request, the corresponding Interrupt
Flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT0 in GIMSK is set (one), the MCU will jump to the Interrupt Vector. The
flag is always cleared when the interrupt routine is executed. Alternatively, the flag is
cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configured
as level interrupt.
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and always read as zero.
Timer/Counter Interrupt Mask
Register – TIMSK
• Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$005) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set
in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 6 – OCIE1: Timer/Counter1 Output Compare Match Interrupt Enable
When the OCIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare Match Interrupt is enabled. The corresponding interrupt (at
vector $004) is executed if a compare match in Timer/Counter1 occurs, i.e., when the
OCF1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
• Bits 5, 4 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and always read as zero.
• Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt
(at vector $003) is executed if a capture-triggering event occurs on pin 14, PB0 (ICP),
i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the AT90S4433 and always reads as zero.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$006) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the AT90S4433 and always reads as zero.
Bit 7 6 5 4 3 2 1 0
$39 ($59) TOIE1 OCIE1 ––TICIE1 – TOIE0 – TIMSK
Read/Write R/W R/W R R R/W R R/W R
Initial Value 0 0 0 0 0 0 0 0