Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
23
AT90S/LS4433
1042G–AVR–09/02
Note: 1. Or external Power-on Reset.
This table shows the Start-up times from Reset. From sleep, only the clock counting part
of the Start-up time is used. The Watchdog Oscillator is used for timing the Real Time
part of the Start-up time. The number WDT Oscillator cycles used for each time-out is
shown in Table 6.
The frequency of the Watchdog Oscillator is voltage dependent, as shown in the Electri-
cal Characteristics section.
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detec-
tion level is nominally 2.2V. The POR is activated whenever V
CC
is below the detection
level. The POR circuit can be used to trigger the Start-up Reset, as well as detect a fail-
ure in supply voltage.
The Power-on Reset (POR) circuit ensures that the device is Reset from Power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-
mines the delay, for which the device is kept in RESET after V
CC
rise. The Time-out
period of the delay counter is a combination of Internal RC Oscillator cycles and Exter-
nal Oscillator cycles, and it can be defined by the user through the CKSEL Fuses. The
eight different selections for the delay period are presented in Table 5. The RESET sig-
nal is activated again, without any delay, when the V
CC
decreases to below detection
level.
Table 5. Reset Delay Selections
CKSEL
[2:0]
Start-up Time,
t
TOUT
at V
CC
=2.7V
Start-up Time,
t
TOUT
at V
CC
= 5.0V Recommended Usage
000 16 ms + 6 CK 4 ms + 6 CK External Clock, slowly rising power
001 6 CK 6 CK External Clock, BOD enabled
(1)
010 256 ms + 16K CK 64 ms + 16K CK Crystal Oscillator
011 16 ms + 16K CK 4 ms + 16K CK Crystal Oscillator, fast rising power
100 16K CK 16K CK Crystal Oscillator, BOD enabled
(1)
101 256 ms + 1K CK 64 ms + 1K CK Ceramic Resonator
110 16 ms + 1K CK 4 ms + 1K CK Ceramic Resonator, fast rising power
111 1K CK 1K CK Ceramic Resonator, BOD enabled
(1)
Table 6. Number of Watchdog Oscillator Cycles
Time-out Number of Cycles
4.0 ms (at V
CC
=5.0V) 4K
64 ms (at V
CC
=5.0V) 64K