Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
21
AT90S/LS4433
1042G–AVR–09/02
The most typical program setup for the Reset and Interrupt Vector addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset Handler
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp EXT_INT1 ; IRQ1 Handler
$003 rjmp TIM1_CAPT ; Timer1 Capture Handler
$004 rjmp TIM1_COMP ; Timer1 compare Handler
$005 rjmp TIM1_OVF ; Timer1 Overflow Handler
$006 rjmp TIM0_OVF ; Timer0 Overflow Handler
$007 rjmp SPI_STC; ; SPI Transfer Complete Handler
$008 rjmp UART_RXC ; UART RX Complete Handler
$009 rjmp UART_DRE ; UDR Empty Handler
$00a rjmp UART_TXC ; UART TX Complete Handler
$00b rjmp ADC ; ADC Conversion Complete Interrupt Handler
$00c rjmp EE_RDY ; EEPROM Ready Handler
$00d rjmp ANA_COMP ; Analog Comparator Handler
;
$00e MAIN: ldi r16,low(RAMEND); Main program start
$00f out SP,r16;
$010 <instr> xxx ;
…… ……
Reset Sources The AT90S4433 has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
POT
).
• External Reset. The MCU is reset when a low level is present on the RESET
pin for
more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage (V
CC
) falls below a
certain voltage.
During Reset, all I/O Registers are then set to their Initial Values, and the program starts
execution from address $000. The instruction placed in address $000 must be an RJMP
(relative jump) instruction to the reset handling routine. If the program never enables an
interrupt source, the Interrupt Vectors are not used, and regular program code can be
placed at these locations. The circuit diagram in Figure 24 shows the Reset Logic. Table
4 and Table 5 define the timing and electrical parameters of the reset circuitry.