Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
13
AT90S/LS4433
1042G–AVR–09/02
I/O Direct Figure 12. I/O Direct Addressing
Operand address is contained in six bits of the instruction word. n is the destination or
source register address.
Data Direct Figure 13. Direct Data Addressing
A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr spec-
ify the destination or source register.
Data Indirect with
Displacement
Figure 14. Data Indirect with Displacement
Operand address is the result of the Y- or Z-register contents added to the address con-
tained in six bits of the instruction word.
OP Rr/Rd
16
31
15 0
16 LSBs
$0000
$00DF
20 19
Data Space
Data Space
$0000
$00DF
Y OR Z - REGISTER
OP an
0
05610
15
15