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AT90C8534

decremented by 2 when data is pushed onto the stack with subroutine RCALL and interrupt. The Stack Pointer is incre-

mented by 1 when data is popped from the stack with the POP instruction and it is incremented by 2 when data is popped

from the stack with return from subroutine RET or return from interrupt RETI.

Reset and Interrupt Handling

The AT90C8534 provides six different interrupt sources. These interrupts and the separate reset vector each have a

separate program vector in the program memory space. All interrupts are assigned individual enable bits that must be set

(one) together with the I-bit in the status register in order to enable the interrupt.

The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The

complete list of vectors is shown in Table 2. The list also determines the priority levels of the different interrupts. The lower

the address, the higher the priority level. RESET has the highest priority and next is INT0 (the External Interrupt Request

0), etc.

The most typical program setup for the Reset and Interrupt vector addresses are:

Address Labels Code Comments

$000 rjmp RESET ; Reset Handler

$001 rjmp EXT_INT0 ; IRQ0 Handler

$002 rjmp EXT_INT1 ; IRQ1 Handler

$003 rjmp TIM1_OVF ; Timer1 Overflow Handler

$004 rjmp TIM0_OVF ; Timer0 Overflow Handler

$005 rjmp ADC ; ADC Conversion Complete Interrupt Handler

$006 rjmp EE_RDY ; EEPROM Ready Handler

;

$007 MAIN: ldi r16, high(RAMEND); Main program start

out SPH, r16

ldi r16, low(RAMEND)

out SPL, r16

<instr> xxx

…………

Table 2. Reset and Interrupt Vectors

Vector No. Program Address Source Interrupt Definition

1 $000 RESET Hardware Pin

2 $001 INT0 External Interrupt Request 0

3 $002 INT1 External Interrupt Request 1

4 $003 TIMER1 OVF Timer/Counter1 Overflow

5 $004 TIMER0 OVF Timer/Counter0 Overflow

6 $005 ADC ADC Conversion Complete

7 $006 EE_RDY EEPROM Ready