Manual

142
AT89C5131
4136A–USB–03/03
Table 94. UEPINT Register
UEPINT (S:F8h read-only)
USB Endpoint Interrupt Register
Reset Value = 00h
76543210
- EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
Bit Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is always 0. Do not set this bit.
6EP6INT
Endpoint 6 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
5EP5INT
Endpoint 5 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
4EP4INT
Endpoint 4 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
3EP3INT
Endpoint 3 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
2EP2INT
Endpoint 2 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
1EP1INT
Endpoint 1 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.
0EP0INT
Endpoint 0 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 89 on
page 138) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 95 on
page 143).
This bit is cleared by software.