Manual

AT86RF401

1424D–RKE–09/02

Watchdog Timer When enabling the watchdog timer, the status of the watchdog time is unknown. The

user is advised to execute a WDR instruction before enabling the watchdog. Otherwise,

the device might get reset before the first WDR after enabling is reached. To prevent the

unintentional disabling of the watchdog, a special turn-off procedure must be followed

when the watchdog is disabled. Refer to the description of the Watchdog Timer Control

prescaler determines the number of system clocks that occur before the watchdog reset

is asserted. The system clock is determined by Bits[7:5] of the AVR_CONFIG register.

Reset and Interrupt

Handling

The AT86RF401 Reset and Interrupt vectors are defined in Table 4. The I-bit in the sta-

tus register must be set to enable the interrupts.

The most typical and general program setup for the Reset and Interrupt Vector

Addresses are:

Reset Sources The AT86RF401 has several sources of reset:

• Power-on Reset: The device is reset when the supply voltage is applied between the

VDD and GND pins. There are 10

cycles of delay between Power-on Reset

occurring and the part becoming active. This is to ensure that the power is stable.

• External Reset: The device is reset when a logic low level is present on the RESETB

pin. This resets all I/O Registers and puts the part into SPI mode. The I/O Registers

may be read and written by the SPI interface after two AVR System Clocks.

• Watchdog Reset: This is similar to power-on reset but is caused by the watchdog

timer and does not have a 10

cycle delay prior to becoming active.

• Brown-out Reset: This is caused by the battery voltage dropping below the Brown-

out Threshold voltage trip point.

• Button Reset (software reset): The part is placed into a special reset state by

software. The part is released from reset when a properly configured button is

activated, and the part is not in external reset or brown-out reset. In the button reset

state, most I/O registers are not reset.

Table 4. Reset and Interrupt Vectors

Vector

Number

Program

Address Source Interrupt Definition

1 $000 RESETB, Watchdog, Buttons Hardware Pin or Watchdog or

Button Reset

2 $002 Transmission Done (TXDONE) Bit Timer Flag 2 Interrupt

4 $004 Transmit Buffer Empty Bit Timer Flag 0 Interrupt

Address Labels Code Comments

$000 jmp RESET ; Reset handler

$002 jmp BT_F2_ISR ; Bit timer flag 2 interrupt service routine

$004 jmp BT_F0_ISR ; Bit timer flag 0 interrupt service routine

$006 MAIN: <instr> xxx ; Main program start

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