User Manual

71
8111A–AVR–05/08
AT86RF231
Note: 1. FORCE_PLL_ON is not valid for states SLEEP, P_ON, RESET, TRX_OFF, and all *_NOCLK
states, as well as STATE_TRANSITION_IN_PROGRESS towards these states.
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi purpose register to control various operating modes and
settings of the radio transceiver.
• Bit 7 - PA_EXT_EN
Refer to Section 11.5 “RX/TX Indicator” on page 147.
• Bit 6 - IRQ_2_EXT_EN
Refer to Section 11.6 “RX Frame Time Stamping” on page 150.
• Bit 5 - TX_AUTO_CRC_ON
If set, register bit TX_AUTO_CRC_ON enables the automatic FCS generation. For further
details refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85.
• Bit 4 - RX_BL_CTRL
Refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152.
• Bit [3:2] - SPI_CMD_MODE
Refer to Section 6.3 “Radio Transceiver Status information” on page 24.
• Bit 1 - IRQ_MASK_MODE
Refer to Section 6.6 “Interrupt Logic” on page 29.
• Bit 0 - IRQ_POLARITY
Refer to Section 6.6 “Interrupt Logic” on page 29.
Register 0x17 (XAH_CTRL_1):
The XAH_CTRL_1 register is a control register for Extended Operating Mode.
• Bit [7:6] - Reserved
• Bit 5 - AACK_FLTR_RES_FT
This register bit shall only be set if AACK_UPLD_RES_FT = 1.
Bit 7 6 5 4 3 2 1 0
+0x04 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON RX_BL_CTRL SPI_CMD_MODE IRQ_MASK_MODE IRQ_POLARITY TRX_CTRL_1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value 0 0 1 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x17 Reserved AACK_FLTR_RES_FT AACK_UPLD_RES_FT Reserved AACK_ACK_TIME AACK_PROM_MODE Reserved XAH_CTRL_1
Read/Write R/W R R/W R/W R R/W R/W R
Reset Value 0 0 0 0 0 0 0 0