User Manual

8111A–AVR–05/08

AT86RF231

Section 7.2.3 “RX_AACK_ON - Receive with Automatic ACK” on page 51 and Section 7.2.4

“TX_ARET_ON - Transmit with Automatic Retry and CSMA-CA Retry” on page 64.

Notes: 1. Even though the reset value for register bits TRAC_STATUS is 0, the RX_AACK and

TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when it is started.

TX_ARET

RX_AACK

• Bit [4:0] - TRX_CMD

A write access to register bits TRX_CMD initiate a radio transceiver state transition:

Table 7-16. TRAC_STATUS Transaction Status

TRAC_STATUS 0

(1)

SUCCESS X X

1 SUCCESS_DATA_PENDING X

2 SUCCESS_WAIT_FOR_ACK X

3 CHANNEL_ACCESS_FAILURE X

5NO_ACK X

(1)

INVALID X X

All other values are reserved

SUCCESS_DATA_PENDING:

Indicates a successful reception of an ACK frame with

frame pending bit set to 1.

SUCCESS_WAIT_FOR_ACK:

Indicates an ACK frame is about to sent in RX_AACK

slotted acknowledgement. Slotted acknowledgement

operation must be enabled with register bit

SLOTTED_OPERATION (register 0x2C, XAH_XTRL_0).

The microcontroller must pulse pin 11 (SLP_TR) at the next

back-off slot boundary in order to initiate a transmission of

the ACK frame. For details refer to IEEE 802.15.4-2006,

section 5.5.4.1.

Table 7-17. State Control Register

TRX_CMD 0x00

NOP

0x02 TX_START

0x03 FORCE_TRX_OFF

0x04

(1)

FORCE_PLL_ON

0x06 RX_ON

0x08 TRX_OFF (CLK Mode)

0x09 PLL_ON (TX_ON)

0x16 RX_AACK_ON

0x19 TX_ARET_ON

All other values are reserved and mapped to NOP