User Manual

166
8111A–AVR–05/08
AT86RF231
14. Register Summary
The AT86RF231 provides a register space of 64 8-bit registers, used to configure, control and
monitor the radio transceiver.
Note: All registers not mentioned within the following table are reserved for internal use and must not be
overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset
value.
Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Page
0x00 - - - - - - - - - -
0x01 TRX_STATUS CCA_DONE CCA_STATUS - TRX_STATUS[4] TRX_STATUS[3] TRX_STATUS[2] TRX_STATUS[1] TRX_STATUS[0] 44,68,97
0x02 TRX_STATE TRAC_STATUS[1] TRAC_STATUS[0] TRAC_STATUS[0] TRX_CMD[4] TRX_CMD[3] TRX_CMD[2] TRX_CMD[1] TRX_CMD[0] 33,44,68
0x03 TRX_CTRL_0 PAD_IO[1] PAD_IO[0] PAD_IO[1] PAD_IO_CLKM[0] CLKM_SHA_SEL CLKM_CTRL[2] CLKM_CTRL[1] CLKM_CTRL[0] 8,118,
0x04 TRX_CTRL_1 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON RX_BL_CTRL SPI_CMD_MODE[1] SPI_CMD_MODE[0] IRQ_MASK_MODE IRQ_POLARITY 24,30,148
0x05 PHY_TX_PWR PA_BUF_LT[1] PA_BUF_LT[0] PA_LT[1] PA_LT[0] TX_PWR[3] TX_PWR[2] TX_PWR[1] TX_PWR[0] 105
0x06 PHY_RSSI RX_CRC_VALID RND_VALUE[1] RND_VALUE[0] RSSI[4] RSSI[3] RSSI[2] RSSI[1] RSSI[0] 90,136
0x07 PHY_ED_LEVEL ED_LEVEL[7] ED_LEVEL[6] ED_LEVEL[5] ED_LEVEL[4] ED_LEVEL[3] ED_LEVEL[2] ED_LEVEL[1] ED_LEVEL[0] 93
0x08 PHY_CC_CCA CCA_REQUEST CCA_MODE[1] CCA_MODE[0] CHANNEL[4] CHANNEL[3] CHANNEL[2] CHANNEL[1] CHANNEL[0] 97
0x09 CCA_THRES - - - - CCA_ED_THRES[3] CCA_ED_THRES[2] CCA_ED_THRES[1] CCA_ED_THRES[0] 97
0x0A RX_CTRL - - - - PDT_THRES[3] PDT_THRES[2] PDT_THRES[1] PDT_THRES[0] 140
0x0B SFD_VALUE SFD_VALUE[7] SFD_VALUE[6] SFD_VALUE[5] SFD_VALUE[4] SFD_VALUE[3] SFD_VALUE[2] SFD_VALUE[1] SFD_VALUE[0] 155
0x0C TRX_CTRL_2 RX_SAFE_MODE - - - - - OQPSK_DATA_RATE[1] OQPSK_DATA_RATE[0] 154
0x0D ANT_DIV ANT_SEL - - - ANT_DIV_EN ANT_EXT_SW_EN ANT_CTRL[1] ANT_CTRL[0] 143
0x0E IRQ_MASK MASK_BAT_LOW MASK_TRX_UR MASK_AMI MASK_CCA_ED_READY MASK_TRX_END MASK_TRX_START MASK_PLL_UNLOCK MASK_PLL_LOCK 30
0x0F IRQ_STATUS BAT_LOW TRX_UR AMI CCA_ED_READY RX_END RX_START PLL_UNLOCK PLL_LOCK 30
0x10 VREG_CTRL AVREG_EXT AVDD_OK - - DVREG_EXT DVDD_OK - - 111
0x11 BATMON - - BATMON_OK BATMON_HR BATMON_VTH[3] BATMON_VTH[2] BATMON_VTH[1] BATMON_VTH[0] 113
0x12 XOSC_CTRL XTAL_MODE[3] XTAL_MODE[2 XTAL_MODE[1 XTAL_MODE[0] XTAL_TRIM[3] XTAL_TRIM[2] XTAL_TRIM[1] XTAL_TRIM[0] 116
0x13 - - - - - - - - -
0x14 - - - - - - - - -
0x15 RX_SYN RX_PDT_DIS - - - RX_PDT_LEVEL[3] RX_PDT_LEVEL[2] RX_PDT_LEVEL[1] RX_PDT_LEVEL[0] 103
0x16 - - - - - - - - -
0x17 XAH_CTRL_1 - - AACK_FLTR_RES_FT AACK_UPLD_RES_FT - AACK_ACK_TIME AACK_PROM_MODE - 68,140
0x18 FTN_CTRL FTN_START - - - - - - - 125
0x19 - - - - - - - - -
0x1A PLL_CF PLL_CF_START - - - - - - - 122
0x1B PLL_DCU PLL_DCU_START - - - - - - - 122
0x1C PART_NUM PART_NUM[7] PART_NUM[6] PART_NUM[5] PART_NUM[4] PART_NUM[3] PART_NUM[2] PART_NUM[1] PART_NUM[0] 25
0x1D VERSION_NUM VERSION_NUM[7] VERSION_NUM[6] VERSION_NUM[5] VERSION_NUM[4] VERSION_NUM[3] VERSION_NUM[2] VERSION_NUM[1] VERSION_NUM[0] 25
0x1E MAN_ID_0 MAN_ID_0[7] MAN_ID_0[6] MAN_ID_0[5] MAN_ID_0[4] MAN_ID_0[3] MAN_ID_0[2] MAN_ID_0[1] MAN_ID_0[0] 25
0x1F MAN_ID_1 MAN_ID_1[7] MAN_ID_1[6] MAN_ID_1[5] MAN_ID_1[4] MAN_ID_1[3] MAN_ID_1[2] MAN_ID_1[1] MAN_ID_1[0] 25
0x20 SHORT_ADDR_0 SHORT_ADDR_0[7] SHORT_ADDR_0[6] SHORT_ADDR_0[5] SHORT_ADDR_0[4] SHORT_ADDR_0[3] SHORT_ADDR_0[2] SHORT_ADDR_0[1] SHORT_ADDR_0[0] 76
0x21 SHORT_ADDR_1 SHORT_ADDR_1[7] SHORT_ADDR_1[6] SHORT_ADDR_1[5] SHORT_ADDR_1[4] SHORT_ADDR_1[3] SHORT_ADDR_1[2] SHORT_ADDR_1[1] SHORT_ADDR_1[0] 76
0x22 PAN_ID_0 PAN_ID_0[7] PAN_ID_0[6] PAN_ID_0[5] PAN_ID_0[4] PAN_ID_0[3] PAN_ID_0[2] PAN_ID_0[1] PAN_ID_0[0] 76
0x23 PAN_ID_1 PAN_ID_1[7] PAN_ID_1[6] PAN_ID_1[5] PAN_ID_1[4] PAN_ID_1[3] PAN_ID_1[2] PAN_ID_1[1] PAN_ID_1[0] 76
0x24 IEEE_ADDR_0 IEEE_ADDR_0[7] IEEE_ADDR_0[6] IEEE_ADDR_0[5] IEEE_ADDR_0[4] IEEE_ADDR_0[3] IEEE_ADDR_0[2] IEEE_ADDR_0[1] IEEE_ADDR_0[0] 76
0x25 IEEE_ADDR_1 IEEE_ADDR_1[7] IEEE_ADDR_1[6] IEEE_ADDR_1[5] IEEE_ADDR_1[4] IEEE_ADDR_1[3] IEEE_ADDR_1[2] IEEE_ADDR_1[1] IEEE_ADDR_1[0] 76
0x26 IEEE_ADDR_2 IEEE_ADDR_2[7] IEEE_ADDR_2[6] IEEE_ADDR_2[5] IEEE_ADDR_2[4] IEEE_ADDR_2[3] IEEE_ADDR_2[2] IEEE_ADDR_2[1] IEEE_ADDR_2[0]
76
0x27 IEEE_ADDR_3 IEEE_ADDR_3[7] IEEE_ADDR_3[6] IEEE_ADDR_3[5] IEEE_ADDR_3[4] IEEE_ADDR_3[3] IEEE_ADDR_3[2] IEEE_ADDR_3[1] IEEE_ADDR_3[0] 76
0x28 IEEE_ADDR_4 IEEE_ADDR_4[7] IEEE_ADDR_4[6] IEEE_ADDR_4[5] IEEE_ADDR_4[4] IEEE_ADDR_4[3] IEEE_ADDR_4[2] IEEE_ADDR_4[1] IEEE_ADDR_4[0] 76
0x29 IEEE_ADDR_5 IEEE_ADDR_5[7] IEEE_ADDR_5[6] IEEE_ADDR_5[5] IEEE_ADDR_5[4] IEEE_ADDR_5[3] IEEE_ADDR_5[2] IEEE_ADDR_5[1] IEEE_ADDR_5[0] 76
0x2A IEEE_ADDR_6 IEEE_ADDR_6[7] IEEE_ADDR_6[6] IEEE_ADDR_6[5] IEEE_ADDR_6[4] IEEE_ADDR_6[3] IEEE_ADDR_6[2] IEEE_ADDR_6[1] IEEE_ADDR_6[0] 76
0x2B IEEE_ADDR_7 IEEE_ADDR_7[7] IEEE_ADDR_7[6] IEEE_ADDR_7[5] IEEE_ADDR_7[4] IEEE_ADDR_7[3] IEEE_ADDR_7[2] IEEE_ADDR_7[1] IEEE_ADDR_7[0] 76
0x2C XAH_CTRL_0 MAX_FRAME_RETRES[3] MAX_FRAME_RETRES[2] MAX_FRAME_RETRES[1] MAX_FRAME_RETRES[0] MAX_CSMA_RETRES[2] MAX_CSMA_RETRES[1] MAX_CSMA_RETRES[0] SLOTTED_OPERATION 68