User Manual

153

8111A–AVR–05/08

AT86RF231

11.7.2 Register Description

The TRX_CTRL_1 register is a multi purpose register to control various operating modes and

settings of the radio transceiver.

• Bit 7 - PA_EXT_EN

Refer to Section 11.5 “RX/TX Indicator” on page 147.

• Bit 6 - IRQ_2_EXT_EN

Refer to Section 11.6 “RX Frame Time Stamping” on page 150.

• Bit 5 - TX_AUTO_CRC_ON

Refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85.

• Bit 4 - RX_BL_CTRL

If this register bit is set the Frame Buffer Empty Indicator is enabled. After sending a Frame

Buffer read command, refer to Section 6.2 “SPI Protocol” on page 19, pin 24 (IRQ) indicates to

the microcontroller that an access to the Frame Buffer is not possible since valid PSDU data are

missing.

Pin IRQ does not indicate any interrupts during this time.

• Bit [3:2] - SPI_CMD_MODE

Refer to Section 6.3 “Radio Transceiver Status information” on page 24.

• Bit 1 - IRQ_MASK_MODE

Refer to Section 6.6 “Interrupt Logic” on page 29.

• Bit 0 - IRQ_POLARITY

Refer to Section 6.6 “Interrupt Logic” on page 29.

Bit 7 6 5 4 3 2 1 0

+0x04 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON RX_BL_CTRL SPI_CMD_MODE IRQ_MASK_MODE IRQ_POLARITY TRX_CTRL_1

Read/Write R/W R/W R/W R/W R/W R/W R/W

Reset Value 0 0 1 0 0 0 0

Table 11-16. Frame Buffer Empty Indicator

RX_BL_CTRL 0

Frame Buffer Empty Indicator disabled

1 Frame Buffer Empty Indicator enabled