User Manual

151
8111A–AVR–05/08
AT86RF231
11.6.2 Register Description
Register 0x04 (TRX_CTRL_1):
Register 0x04 (TRX_CTRL_1) is a multi purpose register to control various operating modes and
settings of the radio transceiver.
• Bit 7 - PA_EXT_EN
Refer to Section 11.5 “RX/TX Indicator” on page 147.
• Bit 6 - IRQ_2_EXT_EN
If this register bit is set the RX Frame Time Stamping Mode is enabled. An incoming frame with
a valid PHR is signaled via pin 10 (DIG2). The pin remains at high level until the end of the frame
receive procedure, see Figure 11-12 on page 150.
Do not enable RX Frame Time Stamping (IRQ_2_EXT_EN = 1) and Antenna Diversity
(ANT_EXT_SW_EN = 1) at the same time, see Section 11.4 “Antenna Diversity” on page 142.
• Bit 5 - TX_AUTO_CRC_ON
Refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85.
• Bit 4 - RX_BL_CTRL
Refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152.
• Bit [3:2] - SPI_CMD_MODE
Refer to Section 6.3 “Radio Transceiver Status information” on page 24.
• Bit 1 - IRQ_MASK_MODE
Refer to Section 6.6 “Interrupt Logic” on page 29.
• Bit 0 - IRQ_POLARITY
Refer to Section 6.6 “Interrupt Logic” on page 29.
Bit 7 6 5 4 3 2 1 0
+0x04 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON RX_BL_CTRL SPI_CMD_MODE IRQ_MASK_MODE IRQ_POLARITY TRX_CTRL_1
Read/Write R/W R/W R/W R/W R/W R/W R/W
Reset Value 0 0 1 0 0 0 0