User Manual

144
8111A–AVR–05/08
AT86RF231
• Bit [3:0] - PDT_THRES
These register bits control the sensitivity of the receiver correlation unit. If the Antenna Diversity
algorithm is enabled, the value shall be set to PDT_THRES = 3, otherwise it shall be set back to
the reset value.
Register 0x0D (ANT_DIV):
The ANT_DIV register controls Antenna Diversity.
• Bit 7 - ANT_SEL
This register bit signals the currently selected antenna path. The selection may be based either
on the last antenna diversity cycle (ANT_DIV_EN = 1) or on the content of register bits
ANT_CTRL, for details refer to Section 11.4.2 “Antenna Diversity Application Example” on page
142.
• Bit [6:4] - Reserved
• Bit 3 - ANT_DIV_EN
If register bit ANT_DIV_EN is set, the Antenna Diversity algorithm is enabled. On reception of a
frame the algorithm selects an antenna autonomously during SHR search. This selection is kept
until:
• A new SHR search starts
• Leaving receive states
• Manually programmed register bits ANT_CTRL
Table 11-10. Receiver Sensitivity Control
Register Bit Value Description
PDT_THRES 0x7
Reset value, to be used if Antenna Diversity algorithm is disabled
0x3 Recommended correlator threshold for Antenna Diversity operation
Other Reserved
Bit 7 6 5 4 3 2 1 0
+0x0D ANT_SEL Reserved ANT_DIV_EN ANT_EXT_SW_EN ANT_CTRL ANT_DIV
Read/Write R R R R R/W R/W R/W R/W
Reset Value 0 0 0 0 0 0 1 1
Table 11-11. Antenna Diversity - Antenna Status
Register Bit Value Description
ANT_SEL 0
Antenna 0
1 Antenna 1