User Manual

140
8111A–AVR–05/08
AT86RF231
Figure 11-9. High Data Rate AACK Timing
If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set the acknowledgment time
is reduced from 192 µs to 32 µs.
11.3.6 Register Description
Register 0x0C (TRX_CTRL_2):
The TRX_CTRL_2 register controls the data rate setting
• Bit 7 - RX_SAFE_MODE
Refer to Section 11.8.2 “Register Description” on page 154.
• Bit [6:2] - Reserved
• Bit [1:0] - OQPSK_DATA_RATE
A write access to these register bits sets the OQPSK PSDU data rate used by the radio trans-
ceiver. The reset value OQPSK_DATA_RATE = 0 is the PSDU data rate according to IEEE
802.15.4.
0
time [µs]
192
512
AACK_ACK_TIME = 0 PSDU: 80 octets
SFD
PHR
SFD
PHR
704 916
32 µs
PSDU: 80 octets
SFD
PHR
SFD
PHR
192 µs
544
AACK_ACK_TIME = 1
ACK
ACK
Bit 7 6 5 4 3 2 1 0
+0x0C RX_SAFE_MODE Reserved OQPSK_DATA_RATE TRX_CTRL_2
Read/Write R/W R R R R R R/W R/W
Reset Value 0 0 0 0 0 0 0 0
Table 11-9. OQPSK Data Rate
Register Bits Value OQPSK Data Rate Comment
OQPSK_DATA_RATE 0
250 kb/s IEEE 802.15.4 compliant
1500 kb/s
2 1000 kb/s
3 2000 kb/s