User Manual

119
8111A–AVR–05/08
AT86RF231
• Bit 3 - CLKM_SHA_SEL
Register bit CLKM_SHA_SEL defines if a new clock rate, defined by CLKM_CTRL, is set imme-
diately or after the next SLEEP cycle.
• Bit [2:0] - CLKM_CTRL
These register bits set clock rate of pin 17 (CLKM).
Register 0x12 (XOSC_CTRL):
The register XOSC_CTRL controls the operation of the crystal oscillator.
• Bit [7:4] - XTAL_MODE
These register bits set the operating mode of the crystal oscillator. For normal operation the
default value is set to XTAL_MODE = 0xF
after reset. Using an external clock source it is recom-
mended to set XTAL_MODE = 0x4.
Table 9-13. CLKM Clock Rate Update Scheme
Register Bit Value Description
CLKM_SHA_SEL 0 CLKM clock rate change appears immediately
1 CLKM clock rate change appears after SLEEP cycle
Table 9-14. Clock Rate Setting at pin CLKM
Register Bit Value Description
CLKM_CTRL 0 No clock at pin 17 (CLKM), pin set to logic low
1
1 MHz
22 MHz
34 MHz
48 MHz
516 MHz
6250 kHz
7 62.5 kHz (IEEE 802.15.4 symbol rate)
Bit
765 4 3 210
+0x12 XTAL_MODE XTAL_TRIM XOSC_CTRL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 1 1 1 1 0 0 0 0
Table 9-15. Crystal Oscillator Operating Mode
Register Bit Value Description
XTAL_MODE 0x4 Internal crystal oscillator disabled, use external reference frequency
0xF Internal crystal oscillator enabled
XOSC voltage regulator enabled