Manual

40
AT86RF230
5131A-ZIGB-06/14/06
Bit Field Name Reset R/W Comments
7:0 IEEE_ADDR_3 0 R/W 8 bits of IEEE address for address recognition, bits[31:24]
Table 8-29. 0x27 - IEEE_ADDR_3
Bit Field Name Reset R/W Comments
7:0 IEEE_ADDR_4 0 R/W 8 bits of IEEE address for address recognition, bits[39:32]
Table 8-30. 0x28 - IEEE_ADDR_4
Bit Field Name Reset R/W Comments
7:0 IEEE_ADDR_5 0 R/W 8 bits of IEEE address for address recognition, bits[47:40]
Table 8-31. 0x29 - IEEE_ADDR_5
Bit Field Name Reset R/W Comments
7:0 IEEE_ADDR_6 0 R/W 8 bits of IEEE address for address recognition, bits[55:48]
Table 8-32. 0x2A - IEEE_ADDR_6
Bit Field Name Reset R/W Comments
7:0 IEEE_ADDR_7 0 R/W Higher 8 bits of IEEE address for address recognition, bits[63:56]
Table 8-33. 0x2B - IEEE_ADDR_7
Bit Field Name Reset R/W Comments
7:4 MAX_FRAME_RETRIES 3 R/W Number of retransmission attempts in ARET mode before the
transaction gets cancelled.
3:1 MAX_CSMA_RETRIES 4 R/W Number of retries in ARET mode to repeat the CSMA/CA procedures
before the ARET procedure gives up.
0 0 R/W Reserved
Table 8-34. 0x2C - XAH_CTRL
Bit Field Name Reset R/W Comments
7:0 CSMA_SEED_0 234 R/W Lower 8 bits of CSMA_SEED, bits[7:0]
Seed for the random number generator in the CSMA/CA algorithm
Table 8-35. 0x2D - CSMA_SEED_0