Manual

53
AT84AD004
5390A–BDC–06/04
Figure 56. Dual ADC and ASIC/FPGA Load Block Diagram
Note: The demultiplexers may be internal to the ASIC/FPGA system.
Port A
Channel I
Port A
Channel Q
Port B
Channel I
Port B
Channel Q
DEMUX
8:16
DMUX
8:16
DMUX
8:16
DMUX
8:16
CLKI/CLKIN @ FsI
CLKQ/CLKQN @ FsQ
Data rate = FsQ/2
Data rate = FsI/2
Data rate = FsQ/4
ASIC / FPGA
Dual 8-bit 1 Gsps ADC