Owner manual

46
AT84AD001B
2153C–BDC–04/04
Figure 50. Simplified Data Ready Reset Buffer Model
Figure 51. Analog Input Model
VCCD/2
100Ω
VCCD
GNDD
DDRB
DDRBN
100Ω
50Ω
50Ω
GND
GND
Vcca
GND
Vcca
Sel Input I
GND
VinI
VinQ
Sel Input Q
VinQ Reverse
Termination
50Ω
ESD
ESD
VinQ
Double
Pad
VinI Double Pad
DC Coupling
(Common Mode = Ground = 0V)
GND – 0.4V
MAX
50Ω
Vinl Reverse
Termination