Owner manual

25
AT84AD001B
2153C–BDC–04/04
Figure 18. Typical DNL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input)
Typical Step Response Figure 19. Step Response
• Fs = 1 Gsps
• Pclock = 0 dBm
• Fin = 100 MHz
•Pin = -1 dBFS
-0,3
-0,2
-0,1
0
0,1
0,2
0,3
1 16 31 46 61 76 91 106 121 136 151 166 181 196 211 226 241 256
Codes
DNL (Lsb)
0
50
100
150
200
250
2.4E-12 1.3E-09 2.5E-09 3.8E-09 5.0E-09 6.3E-09 7.5E-09 8.8E-09
Time (s)
Codes
Channel IA Channel QA