User Manual

6
4234F–SCR–10/05
AT83C24
Operational Modes
TWI Bus Control The Atmel Two-wir e Interface ( TWI) interconn ects componen ts on a uniq ue two-wire bus, made
up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a
byte-oriented transfer format.
The TWI-bus interface can be used:
– To configure the AT83C24
– To select the operating mode of the card: 1.8V, 3V or 5V
– To configure the automatic activation sequence
– To start or stop sessions (activation and de-activation sequences)
– To initiate a warm reset
– To contr ol th e cloc k to the car d in ac tive mode
– To control the clock to the card in stand-by mode (stop LOW, stop HIGH or running)
– To enter or leave the card stand-by or power-down modes
– To select the interface (connection to th e host I/O / C4/ C8)
– To request the status (car d present or not, over-current and out of range supply
voltage occurrence)
– To drive an d mon ito r th e car d co ntacts by software
– To accurately measure the ATR delay when automatic activation is used
TWI Commands
Frame Structure The structure of the TWI bus data frames is made of one or a series of write and read com-
mands completed by STOP.
Write commands to the AT83C24 have the structure:
ADDRESS BYTE + COMMAND BYTE + DATA BYTE(S)
Read commands to the AT83C24 have the structure:
ADDRESS BYTE + DATA BYTE(S)
The ADDRESS BYTE is sampled on A2/CK, A1/RST, A0/3V after each re set (hard/soft/general
call) but A2/CK, A1/RST, A0/3V can be used for transparent mode after the reset.
Figure 1. Data transfer on TWI bus
SDA
SCL
start condition
stop condition
1234
5
6
78
9
acknowledgement
from slave
Adresse byte
command
and/or data