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Features

• Smart Card Interface

– Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL Standards

Card Clock Stop High or Low for Card Power-down Modes

Support Synchronous Cards with C4 and C8 Contacts

Card Detection and Automatic de-activation Sequence

Programmable Activation Sequence

– Direct Connection to the Smart Card

Logic Level Shifters

Short Circuit Current Limita tion (see electrical characteristics)

8kV+ ESD Protection (MIL/STD 883 Class 3)

– Programmable Voltage

5V ±5% at 65 mA (Class A)

3V ±0.2V at 65 mA (C la ss B)

1.8V ±0.14V at 40 mA

– Low Ripple Noise: < 200 mV

• Versatile Ho st Interf ace

– ICAM (Conditional Access) Compatible

– Two Wire Interface (TWI) Link

Programmable Address Allow up to 8 Devices

– Programmable Interrupt Output

– Automatic Level Shifter (1.6V to V

)

• Reset Output Includes

– Power-On Reset (POR)

– Power-Fail Detector (PFD)

• High-efficiency Step-up Converter: 80 to 98% Efficiency

• Extended Voltage Operation: 3V to 5.5V

• Low Power Consumption

– 180 mA Maximum In-rush Current

– 30 μA Typical Power-down Current (without Smart Card)

• 4 to 48 MHz Clock Input, 7 MHz Min for Step-up Converter (for AT83C24)

• 18 to 48MHz Clock input (for AT83C24NDS)

• Industrial Temperat ure Range: -40 to +85°C

• Packages: SO28 and QF N28

Description

The AT83C2 4 is a sm art c ard reade r inte rfac e IC for smart card reader/writer applica -

tions such as EFT/POS te rminals and set top boxes. It enab les the management of

any type of sma rt card from any kind of host. Up to 8 AT 83C24 can be conne cted in

parallel using the programmable TWI address.

Its high efficiency DC/DC converter, low quiescent current in standby mode makes it

particularly suited to low power and portable applications. The reduced bill of material

allows reducing significantly the system cost. A sophisticated protection system guar

antees timely and controlled shutdown upon error conditions.

The AT83C24NDS is a dedicated version approved by NDS for use with NDS Video-

Guard conditional access software in set-top boxes. All AT83C24 datasheet is

applicable to AT83C24NDS. The main differences between AT83C24 and

AT83C24NDS are listed below:

1/ CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS,

CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24

2/ 18MHz minimum on input clock for AT 83C24NDS

3/ Up to 10µF for capacitor connected on CVCC pin for AT83C24,

3.3µF mandatory for AT83C24NDS

Smart Card

Reader

Interface with

Power

Management

AT83C24B

AT83C24NDS

4234F–SCR–10/05

Summary of content (42 pages)

PAGE 1
Features • Smart Card Interface • • • • • • • • • – Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL Standards Card Clock Stop High or Low for Card Power-down Modes Support Synchronous Cards with C4 and C8 Contacts Card Detection and Automatic de-activation Sequence Programmable Activation Sequence – Direct Connection to the Smart Card Logic Level Shifters Short Circuit Current Limitation (see electrical characteristics) 8kV+ ESD Protection (MIL/STD 883 Class 3) – Programmable Voltage 5V ±5% at 65
PAGE 2
Acronyms TWI: Two-wire Interface POR: Power On Reset PFD: Power Fail Detect ART: Automatic Reset Transition ATR: Answer To Reset MSB: Most Significant Bit LSB: Least Significant bit SCIB: Smart Card Interface Bus Block Diagram VCC DVCC EVCC RESET VSS CVSS LI CVCC Voltage supervisor POR/PFD DC/DC Converter CVCCIN PRES/ INT A2/CK, A1/RST, A0/3V, CMDVCC SCL SDA TWI Controller Main Control & Logic Unit Timer 16 Bits Clocks Controller CLK Analog Drivers CPRES CRST CIO, CC4, CC8 I/O, C4, C8 2
PAGE 3
AT83C24 Pin Description 6 CVSS LI 7 8 22 21 CVCC CVCCin EVCC A2/CK A1/RST VSS VCC 3 CVSS 4 A0 /3V 9 20 10 19 SCL SDA CRST 11 18 NC CCLK 17 CIO NC 12 13 16 CC8 CC4 14 15 CPRES LI CVCC CVCCin C4 I/O CLK 28 27 26 25 24 23 22 1 21 20 2 19 QFN 28 EVCC A2 /CK A1 /RST 18 A0 /3V 5 17 SCL 6 16 TOP VIEW 8 SDA 15 NC 9 10 11 12 13 14 7 CIO VCC 24 23 5 CMDVCC CC8 25 PRES/INT PRES/INT C4 I/O CPRES 3 4 C8 RESET NC CLK 27 26 CC4 28 2 RESET 1 CCLK C8
PAGE 4
Table 1. Ports Description (Continued) Pad Name Pad Internal Power Supply SDA VCC SCL VCC ESD Limits 3 kV 3 kV Pad Type I/O opendrain I/O opendrain Description Microcontroller Interface Function TWI serial data Microcontroller Interface Function TWI serial clock Microcontroller Interface Function I/O EVCC 3 kV Copy of CIO pin and high level reference for EVCC. I/O An external pull up to EVCC is needed on IO pin. I/O is the reference level for EVCC if EVCC is connected to a capacitor.
PAGE 5
AT83C24 Table 1. Ports Description (Continued) Pad Name Pad Internal Power Supply ESD Limits Pad Type 8 kV+ PWR Description Card Supply Voltage CVCC CVCC is the programmable voltage output for the Card interface. It must be connected to external decoupling capacitors (see page 34 and page 36). CVCCin 8 kV+ PWR Card Supply Voltage This pin must be connected to CVCC. Digital Supply Voltage DVCC 3 kV+ PWR Is internally generated and used to supply the digital core.
PAGE 6
Operational Modes TWI Bus Control The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. The TWI-bus interface can be used: – To configure the AT83C24 – To select the operating mode of the card: 1.
PAGE 7
AT83C24 Address Byte The first byte to send to the device is the address byte. The device controls if the hardware address (A2/CK, A1/RST, A0/3V pins on reset) corresponds to the address given in the address byte (A2, A1, A0 bits). If the level is not stable on A2/CK pin (or A1/RST pin, or A0/3V pin) at reset, the user has to send the commands to the possible address taken by the device.
PAGE 8
Write Commands The write commands are: 1. Reset: Initializes all the logic and the TWI interface as after a power-up or power-fail reset. If a smart card is active when RESET falls, a deactivation sequence is performed. This is a onebyte command. 2. Write Config: Configures the device according to the last six bits in the CONFIG0 register and to the following four bytes in CONFIG1, CONFIG2, CONFIG3 then CONFIG4 registers. This is a five bytes command. Figure 3.
PAGE 9
AT83C24 Read Command After the slave address has been configured, the read command allows to read one or several bytes in the following order: • STATUS, CONFIG0, CONFIG1, CONFIG2, CONFIG3, INTERFACE, TIMER1, TIMER0, CAPTURE1, CAPTURE0 • FFh is completing the transfer if the microcontroller attempts to read beyond the last byte. Note: Flags are only reset after the corresponding byte read has been acknowledged by the master. Table 4.
PAGE 10
– over-current detection on CVCC – VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or bit set by software) Card Presence Detection The card presence is provided by the CPRES pin. The polarity of card presence contact is selected with the CARDDET bit (see CONFIG1 register). A programmable filtering is controlled with the CDS[2-0] bits (see CONFIG1 register).
PAGE 11
AT83C24 CIO, CC4, CC8 Controller The CIO, CC4, CC8 output pins are driven respectively by CARDIO, CARDC4, CARDC8 bits values or by I/O, C4, C8 signal pins. This selection depends of the IODIS bit value. If IODIS is reset, data are bidirectional between respectively I/O, C4, C8 pins and CIO, CC4, CC8 pins. Figure 5.
PAGE 12
Figure 6. Clock Block Diagram with Software Activation (see page 14) CLK A2/CK DCCLK DCK[2:0] DC/DC CKS[2:0] 0 CCLK 1 CARDCK bit CKSTOP bit Figure 7. Clock Block Diagram with Hardware Activation (see page 14) CLK A2/CK DCCLK DCK[2:0] DC/DC CKS[2:0] 0 CCLK 1 CARDCK bit CMDVCC Hardware activation A1/RST CKSTOP bit CRST_SEL bit CRST Controller The CRST output pin is driven by the A1/RST pin signal pin or by the CARDRST bit value.
PAGE 13
AT83C24 Figure 8. CRST Block Diagram with soft activation 0 CARDRST bit tb delay 1 see Fig 12 0 ART bit CRST 1 CRST_SEL bit = 0 Figure 9.
PAGE 14
Activation Sequence Hardware Activation (DC/DC started with CMDVCC) Initial conditions: CARDDET bit must be configured in accordance to the smart card connector polarity. IT_SEL bit, CRST_SEL bit (see CONFIG4 register) must be set and CARDRST bit (see INTERFACE register) must be cleared. A smart card must be detected to enable to start the DC/DC (CVCC= 3V or 5V). The hardware activation sequence is started by hardware with CMDVCC pin going high to low.
PAGE 15
AT83C24 Software Activation (DC/DC Started With Writing in VCARD[1:0] bits) and ART bit = 1 Initial conditions: CARDRST bit = 0, CKSTOP bit =1, IODIS bit = 1. The following sequence can be applied: 1. Card Voltage is set by software to the required value (VCARD[1:0] bits in CONFIG0 register). This writing starts the DC/DC. 2. Wait the end of the DC/DC init with a polling on VCARDOK bit (STATUS register) or wait for PRES/INT to go Low if enabled (if IT_SEL bit = 0 in CONFIG4 register).
PAGE 16
ISO 7816 constraints: ta = 200 card clock cycles 400 card clock cycles< = tb 400 card clock cycles< = tc < = 40000 card clock cycles Note: Timer[1-0] reset value is 400. Software Activation (DC/DC Started by Writing in VCARD[1:0] bits) and ART bit = 0 The activation sequence is controlled by software using TWI commands, depending on the cards to support. For ISO 7816 cards, the following sequence can be applied: 1.
PAGE 17
AT83C24 • VCARDERR bit is set by hardware (or by software) • INSERT is set and CARDIN is cleared (card extraction) • SHUTDOWN is set by software • CMDVCC goes from Low to High • Power fail on VCC (see POWERMON bit in CONFIG4 register) • Reset pin going low It is a self-timed sequence which cannot be interrupted when started (see Figure 13). Each step is separated by a delay based on Td equal to 8 periods of the DC/DC clock, typically 2 µs: 1. T0: CARDRST is cleared, SHUTDOWN bit set. 2.
PAGE 18
Figure 14. Transparent Mode Description Microcontroller Power Modes AT83C24 CCLK A2/CK CCLK CRST A1/RST CRST CIO I/O CIO CC4 C4 CC4 CC8 C8 CC8 SMART CARD Two power-down modes are available to reduce the AT83C24 power consumption (see STUTDOWN bit in CONFIG1 register and LP bits in CONFIG3 register). To enter in the mode number 4 (see Table 5), the sequence is the following: – First select the Low-power mode by setting the LP bit – The activation of the SHUTDOWN bit can then be done.
PAGE 19
AT83C24 Power Monitoring The AT83C24 needs only one power supply to run: VCC. If the microcontroller outputs signals with a different electrical level, the host positive supply is connected to EVCC. EVCC and VCC pins can be connected together if they have the same voltage. • If EVCC and VCC have different electrical levels: The EVCC pin and RESET pin should be connected with a resistor bridge. RESET pin high level must be higher than VIH (see Table 19). When EVCC drops, RESET pin level drops too.
PAGE 20
Registers Table 6. CONFIG0 (Config Byte 0) 7 6 5 4 1 0 ATRERR INSERT Bit Number 7-6 3 2 ICARDERR VCARDERR 1 0 VCARD1 VCARD0 Bit Mnemonic Description 1-0 These bits cannot be programmed and are read as 1-0. Answer to Reset Interrupt 5 ATRERR This bit is set when the card clock counter overflows (no falling edge on CIO is received before the overflow of the card clock counter). This bit is cleared by hardware when this register is read. It can be set by software for test purpose.
PAGE 21
AT83C24 Table 7. CONFIG 1 (Config Byte 1) Bit Number 7 7 6 5 4 3 2 1 0 X ART SHUTDOWN CARDDET PULLUP CDS2 CDS1 CDS0 Bit Mnemonic Description X This bit should not be set. Automatic Reset Transition Set this bit to have the CRST pin changed according to activation sequence. 6 ART Clear this bit to have the CRST pin immediately following the value programmed in CARDRST. The reset value is 0. Shutdown 5 SHUTDOWN Set this bit to reduce the power consumption.
PAGE 22
Table 8. CONFIG2 (Config Byte 2) Bit Number 7 7 6 5 4 3 2 1 0 X DCK2 DCK1 DCK0 X CKS2 CKS1 CKS0 Bit Mnemonic Description X This bit should not be set. DC/DC Clock prescaler factor DCCLK is the DC/DC clock. It is the division of CLK input by DCK prescaler. DCK = 0: prescaler factor equals 1 (CLK = 4 to 4.61MHz) DCK [2:0] = 1: prescaler factor equals 2 (CLK = 7 to 9.25MHz) DCK [2:0] = 2: prescaler factor equals 4 (CLK = 14 to 18.
PAGE 23
AT83C24 Table 9. CONFIG3 (Config Byte 3) 7 6 5 4 3 2 1 0 EAUTO VEXT1 VEXT0 ICCADJ LP X X X Bit Number Bit Mnemonic Description EVCC voltage configuration: EAUTO VEXT1 VEXT0 EAUTO 7-5 VEXT1 VEXT0 0 0 0 EVCC = 0 the regulator is switched off. 0 0 1EVCC = 2.3V 0 1 0 EVCC = 1.8V 0 1 1 EVCC = 2.7V 1 X X EVCC voltage is the level detected on I/O input pin.
PAGE 24
Table 10. CONFIG4 (Config Byte 4) 7 6 5 4 3 2 1 0 X X X STEPREG INT_PULLUP POWERMON IT_SEL CRST_SEL Bit Number Bit Mnemonic 7-5 X-X-X Description These bits should not be set. Step Regulator mode Clear this bit to enable the automatic step-up converter (CVCC is stable even if VCC is not higher than CVCC). 4 STEPREG Set this bit to permanently disable the step-up converter (CVCC is stable only if VCC is sufficiently higher than CVCC).
PAGE 25
AT83C24 Table 11. INTERFACE (Interface Byte) 7 6 5 4 3 2 1 0 0 IODIS CKSTOP CARDRST CARDC8 CARDC4 CARDCK CARDIO Bit Number Bit Mnemonic 7 0 Description This bit should not be set. Card I/O isolation 6 IODIS Set this bit to drive the CIO, CC4, CC8 pins according to CARDIO, CARDC4, CARDC8 respectively and to put I/O, C4, C8 in Hi-Z.
PAGE 26
Table 12. STATUS (Status Byte) 7 6 5 4 3 2 1 0 CC8 CC4 CARDIN VCARDOK X VCARD_INT CRST CIO Bit Number Bit Mnemonic 7 CC8 Description Card CC8 This bit provides the actual level on the CC8 pin when read. The reset value is 0. Card CC4 6 CC4 This bit provides the actual level on the CC4 pin when read. The reset value is 0. Card Presence Status 5 CARDIN This bit is set when a card is detected. It is cleared otherwise.
PAGE 27
AT83C24 Table 14. TIMER 0 (Timer LSB) 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Number Bit Mnemonic Description 7-0 bits 7 - 0 Timer LSB (bits 7to 0) Reset value = 0x10010000 Table 15. CAPTURE 1 (Capture MSB) 7 6 5 4 3 2 1 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Bit Number Bit Mnemonic Description 7-0 bits 15 - 8 See “software activation with ART = 1”, page 15. Reset value = 0x00000000 Table 16.
PAGE 28
Electrical Characteristics Absolute Maximum Ratings * *NOTICE: Ambient Temperature Under Bias: .....................-40°C to 85°C Storage Temperature: ................................... -65°C to +150°C Voltage on VCC: ........................................ VSS -0.5V to +6.0V Voltage on SCIB pins (***): ......... CVSS -0.5V to CVCC + 0.5V Voltage on host interface pins:.......VSS -0.5V to EVCC + 0.5V Voltage on other pins: ...................... VSS -0.5V to VCC + 0.
PAGE 29
AT83C24 Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC, PRES/INT) (Continued) Symbol VOL VOH EICC Parameter Min Typ Output Low-voltage (I/O, C4, C8, PRES/INT) Output High Voltage (C4, C8, PRES/INT) VOH on I/O depends on external pull up value 0.8 x EVCC Extra Supply Current Max Unit Test Conditions 0.05 V IOL = -100 μA 0.4 V IOL = -1.2 mA EVCC V +3 mA 360 κΩ EVCC from 1.
PAGE 30
Table 20. Smart Card Class A Symbol Parameter Min Typ Max 60 200 150 350 Unit Test Conditions 0 < Icard < 60mA CL =10µF Ripple on CVCC mV for AT83C24 0 < Icard < 65mA CL = 3.3µF for AT83C24NDS Max. charge 40 nA.s Spikes on CVCC 4.6 5.3 V Max. duration 400 ns Max. Icard variation 200 mA Vcardok up Vcardok high level threshold Vcardok down Vcardok low level threshold 4.8 4.9 4.6 4.8 4.75 4.
PAGE 31
AT83C24 Table 21. Smart Card Class B Symbol Parameter Min Typ Max 140 250 110 250 Unit Test Conditions VCC = 3V, CL = 3.3µF TVLH Icard = 65mA Icard = 0mA μs CVCC 0 to Valid VCC = 3V, CL = 10µF Notes: 130 250 Icard = 60mA 100 250 Icard = 0mA 1. Capacitor: X7R type or X5R type, max ESR value is 30mΩ (100kHz-100MHz), Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction. Table 22.
PAGE 32
Table 23. Smart Card Clock (CCLK pin) (Continued) Symbol Parameter Min Typ Max Unit 0.2 Test Conditions CLASS A CCLK from 0.5 to 4.2V Rise and Fall Slew rate 0.12 V/ns CLASS B CCLK from 0.5 to 0.85 x CVCC Low level voltage stability -0.25 0.5 High level voltage stability 4.2 CVCC+0.25 (taking into account PCB design) 2.35 CVCC+0.25 CVCC-0.4 CVCC+0.
PAGE 33
AT83C24 Table 25. Smart Card RST (CRST pin) Symbol Parameter Min Typ Max Unit 0.12 x CVCC VOL Output Low-voltage 0 0.4 0 Test Conditions IOL = -20 µA CLASS A&B&C V 0.2 IOL = -200 µA CLASS A IOL = -200 µA CLASS B&C VOH Output High Voltage 0.9*CVCC CVCC V IOS Output High Current -15 +15 mA tR tF Rise and Fall time 0.
PAGE 34
Typical Application Figure 1. Typical Standard Mode Application Diagram for 3 AT83C24 (up to 8 AT83C24 if needed) VCC EVCC 100nF L1 4.7µH C1 C13 CRST CIO, CC4, CC8 CPRES CCLK CVCC, AT83C24 CVCCin A0/3V SDA, SCL pullups LI VSS A1/RST CVSS A2/CK See note for I/O pull up VCC VCC EVCC VCC VCC 2.2µF VSS VSS Reset pullup TWI SCL SDA RST RESET Card 1 100nF 2.2uF 1uF C2 C3 C10 CVSS CVSS CVSS INT0 Px.
PAGE 35
PAGE 36
Typical NDS Application Figure 2. Typical NDS Standard Mode Application Diagram for 1 AT83C24NDS. VCC EVCC 100nF L1 4.7µH C1 C13 See note 2 SDA, SCL pullups LI CVSS Reset pullup TWI SCL SDA RST RESET INT0 Px.y VSS See note1 for I/O pull up VCC VCC EVCC VCC CRST CIO, CC4, CC8 CCLK Host MICROCONTROLLER XTAL1 Smart Card 1 PRES/INT I/O, C4, C8 CVCCin CVCC CLK Px.y Px.y Px.y 2.2µF VSS VSS A2/CLK A1/RST A0/3V 1uF 2.
PAGE 37
AT83C24 Ordering Information Part Number Supply Voltage Temperature Range Package Packing AT83C24B-PRTIL(2) 3V to 5.5V Industrial QFN28 Tray AT83C24B-PRRIL(2) 3V to 5.5V Industrial QFN28 Tape&Reel AT83C24B-PRTIM(2) 4.00V to 5.5V Industrial QFN28 Tray AT83C24B-PRRIM(2) 4.00V to 5.5V Industrial QFN28 Tape&Reel AT83C24B-TISIL 3V to 5.5V Industrial SO28 Stick AT83C24B-TIRIL 3V to 5.5V Industrial SO28 Tape&Reel AT83C24B-TISIM 4.00V to 5.
PAGE 38
Note: Part Number Supply Voltage Temperature Range Package Packing AT83C24NDS-TISUL (1) 3V to 5.5V Industrial & Green SO28 Stick AT83C24NDS-TIRUL (1) 3V to 5.5V Industrial & Green SO28 Tape&Reel AT83C24NDS-TISUM (1) 4.00V to 5.5V Industrial & Green SO28 Stick AT83C24NDS-TIRUM (1) 4.00V to 5.5V Industrial & Green SO28 Tape&Reel 1. Enhanced AC/DC parameters, see first page for differences between AT83C24 and AT83C24NDS. 2. Refer to index mark for proper placement.
PAGE 39
AT83C24 Package Drawings QFN28 39 4234F–SCR–10/05
PAGE 40
SO28
PAGE 41
AT83C24 Datasheet Change Log Changes from 4234A-05/03 to 4234B-02/04 1. Addition of CRST, CIO, CCLK controllers descriptions, page 10. 2. Update of Hardware\Software activation description, page 14. 3. Suppression of low voltage regulator mode for power down modes, page 18. 4. Modification of clock values in CONFIG2 regsiter, page 22. 5. Addition of a point on QFN pinout view, page2. 6. Update of electrical characteristics, page 28. Changes from 4234B-02/04 to 4234C - 04/04 1.
PAGE 42
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.