Owner manual

66
AT76C551
1612D–08/01
• Bit 0 – RHR: Receive Holding Register Ready
When set indicates that the Receive Holding Register is full. In order to clear this bit you must
empty the RHR (or the FIFO if it is enabled) by reading the US_RHR register.
Note: Default Value: 00 hex
US_CR: Control Register
addr: 700018 hex R/W 8 bits
• Bit 7 – RXEN: Enable
When set, this enables the receiver block of UART.
• Bit 6 – RLES: Reset Line Error Status bits
When set, this resets the PE, FE, OE bits of US_CSR register.
• Bit 5 – TXEN: Tx Enable
When set, this enables the transmitter block of UART.
• Bit 4 – RSTO: Restart Time-out
When set, this resets the time-out counter for a new time-out period.
• Bit 3 – TXRS: Tx Reset
• When set, this resets the transmit logic.
• Bit 2 – RXRS: Rx Reset
When set, this resets the receive logic.
• Bit 1 – SPB: Stop Break
Break command to the transmit logic. When set, this stops break condition.
• Bit 0 – STB: Start Break
Break command to the transmit logic. When set, this starts break condition.
Note: Default Value: 00 hex
US_BL: Low Byte, Baud Rate Register
addr: 70001C hex R/W 8 bits
• Bits 7..0 – US_BL[7:0]
Baud rate generator division ratio low. The main system clock is divided by the number con-
tained in US_BL and US_BM, to provide the USART clock (which is 16 times the actual serial
data rate).
Note: Default Value: 00 hex
US_BM: High Byte, Baud Rate Register
addr: 700020 hex R/W 8 bits
• Bits 7..0 – US_BM[7:0]
Baud rate generator division ratio high.
Note: Default Value: 00 hex