Owner manual

64
AT76C551
1612D–08/01
US_FCR: FIFO Control Register
addr: 700008 hex R/W 8 bits
• Bits 7..6 RCVR[1:0]a; RCVR Trigger Bits
These bits indicate the minimum number of bytes required in the receive FIFO to generate a
receive ready interrupt.
• Bits 5..4 – Reserved
• Bit 3 – RDMA: DMA Mode Select.
When set the DMA is in burst mode according to the value in US_FCR. When it is cleared the
characters are read one byte each time.
• Bit 2 – Reserved
• Bit 1 – FRS: FIFO Reset
When set, resets the receive FIFO.
• Bit 0 – FEN: FIFO Enable
When set, enables the 16 byte receive FIFO.
Note: Default Value: 00 hex
The trigger level is shown in Table 11.
Protocol Mode Register (US_PMR)
US_PMR: Protocol Mode Register
addr: 70000C hex R/W 8 bits
• Bits 7..6 – CHL[1:0]: Character Length
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits
• Bits 5..4 – SBN[1:0]: Number of Stop Bits
00: 1-bit time
01: 1- ,5-bit time
10: 2-bit time
11: Reserved
• Bits 3..2 – PM[1:0]: Parity Mode
00: Normal parity
01: Parity forced
Table 11. Trigger Level
Bit 7 Bit 6 Trigger Level
00 1
01 4
10 8
11 14