Owner manual

58
AT76C551
1612D–08/01
0 = Disable interrupt
FADDR: Function Address Register
addr 50003C8h R 8 bits
• Bit 7 – FEN: Function Enable
• Bits 6..0 – FADD[6:0]: Function Address
Note: Default: 00h
The FIU address register contains the function address assigned by the Host. This Function
Address Register must be programmed by the processor once it has:
1. Received a SET_ADDRESS command from the Host.
2. Completed the status phase of the transaction. After power up or reset this register will
contain the value of 0x00.
The Function Enable bit (FEN) allows the firmware to enable or disable the function Endpoints.
The firmware will set this bit after receipt of a reset through the USB hardware. Once this bit is
set the USB hardware passes packets to and from the Host.
ENDPPGPG: Endpoint Ping-pong Enable Register
addr 50003C4h R 8 bits
Bit 7 – Reserved
• Bit 6 – PG_EP6_EN:Enable Endpoint 6 Ping-pong
• Bit 5 – PG_EP5_EN: Enable Endpoint 5 Ping-pong
• Bit 4 – PG_EP4_EN: Enable Endpoint 4 Ping-pong
• Bit 3 – PG_EP3_EN: Enable Endpoint 3 Ping-pong
• Bit 2 – PG_EP2_EN: Enable Endpoint 2 Ping-pong
• Bit 1 – PG_EP1_EN: Enable Endpoint 1 Ping-pong
• Bit 0 – PG_EP0_EN: Enable Endpoint 0 Ping-pong
Endpoint Control Registers
addr: see below 8 bits
Endpoint Control Registers
addr: see below 8 bits
• Bit 7 R – EPEDS: Endpoint Enable/Disable
0 = Disable Endpoint
1 = Enable Endpoint
• Bit 6 – Reserved
• Bits 5..4 – Reserved and set to 0
• Bit 3 W – DTGLE: Data Toggle
Identifies DATA0 or DATA1 packets.
• Bit 2 R – EPDIR: Endpoint Direction
Only applicable for non-control Endpoints (0 = Out, 1 = In).
• Bits 1..0 R – EPTYPE: Endpoint Type
These bits represent the type of the Endpoint (see Tables 6, 7, 8 and 9).