Owner manual

57
AT76C551
1612D–08/01
• Bit 7 – Reserved
• Bit 6 – EP6 INT: Endpoint 6 Interrupt
• Bit 5 – EP5 INT: Endpoint 5 Interrupt
• Bit 4 – EP4 INT: Endpoint 4 Interrupt
• Bit 3 – EP3 INT: Endpoint 3 Interrupt
• Bit 2 – EP2 INT: Endpoint 2 Interrupt
• Bit 1 – EP1 INT: Endpoint 1 Interrupt
• Bit 0 – EP0 INT: Endpoint 0 Interrupt
Note: Default: 00h
The function interrupt bits will be set by the hardware whenever the following bits in the corre-
sponding Endpoint’s Control and Status Register are modified by the USB hardware:
1. RX OUT Packet is set (Control and OUT Endpoint).
2. TX Packet Ready is cleared (Control and IN Endpoint).
3. RX SETUP is set (Control Endpoints only).
4. TX Complete is set (Control Endpoints only).
UIAR: USB Interrupt Acknowledge Register
addr 50003D4h W 8 bits
• Bit 7 – Reserved
• Bit 6 – EP6 INTA: Endpoint 6 Interrupt Acknowledge
• Bit 5 – EP5 INTA: Endpoint 5 Interrupt Acknowledge
• Bit 4 – EP4 INTA: Endpoint 4 Interrupt Acknowledge
• Bit 3 – EP3 INTA: Endpoint 3 Interrupt Acknowledge
• Bit 2 – EP2 INTA: Endpoint 2 Interrupt Acknowledge
• Bit 1 – EP1 INTA Endpoint 1 Interrupt Acknowledge
• Bit 0 – EP0 INTA: Endpoint 0 Interrupt Acknowledge
Note: Default: 00h
The bits in this register are used to indirectly clear the bits of the UISR. A bit in the UISR is
cleared if a 1 is written in the corresponding bit of UIAR.
UIER: USB Interrupt Enable Register
addr 50003CCh R/W 8 bits
• Bit 7 – SOFIE: Enable SOF Interrupt
• Bit 6 – EP6 IE: Enable Endpoint 6 Interrupt
• Bit 5 – EP5 IE: Enable Endpoint 5 Interrupt
• Bit 4 – EP4 IE: Enable Endpoint 4 Interrupt
• Bit 3 – EP3 IE: Enable Endpoint 3 Interrupt
• Bit 2 – EP2 IE: Enable Endpoint 2 Interrupt
• Bit 1 – EP1 IE: Enable Endpoint 1 Interrupt
• Bit 0 – EP0 IE:Enable Endpoint 0 Interrupt
Note: Default: 00h
The bits in this register has the following meaning:
1 = Enable interrupt