Owner manual

43
AT76C551
1612D–08/01
• Bits 31..8 – Reserved
• Bits 7..0 – RX_byte[7:0]
Least recent received byte not yet read
Note: Please note that reading RxFifoReadPort register is meaningful only if RX FIFO level is at least
one, i.e. at least one byte exists in RX FIFO.
If RX FIFO is not serviced before it is full it will overflow and subsequent bytes received will be
lost. RX FIFO capacity is 64 bytes.
TxFifoCtrlStatus
addr: 600068 hex R/W 32 bits
• Bits 31..15 – Reserved
• Bit 14 R – Empty
Set by hardware while FIFO is empty
• Bit 13 R – Full
Set by hardware while FIFO is full
• Bit 12 W – Reset
Set by firmware to discard any possible FIFO contents. Auto-clear
• Bits 11..6 R/W – Threshold[5...0]
Set by firmware to define the maximum level at which FIFO is considered “almost empty”.
• Bits 5..0 R – Level[5...0]
Current FIFO level, i.e. number of bytes written into FIFO, waiting to be transmitted.
Note: Default Value: 00000000 hex
TxFifoWritePort
addr: 60006C hex W 32 bits
• Bits 31..8 – Reserved
• Bits 7..0 – TX_byte[7:0]
Next byte to transmit
Note: Writing TxFifoWritePort register is not permitted if TX FIFO is full.
If TX FIFO is not serviced before it is empty it will underflow and transmitted bytes will be lost.
TX FIFO capacity is 64 bytes.
hopSelCtrlStatus
addr: 600070 hex RW 32 bits
Bits 31..4 – Reserved
• Bit 4..3 – Hop_Type
Indicates frequency hop type (page, inquiry, etc.).
• Bit 2 – Hop_Kernel_Direct
0: Hop selection calculation parameters (A,B,.X,Y1,.) are estimated by hardware.
1: Hop selection calculation parameters are provided directly by firmware.
• Bit 1 – Mode_79_23
0: 79 Frequency Hop System