Owner manual

42
AT76C551
1612D–08/01
Clears HEC fail interrupt
• Bit 4 – RxCrcFail_IntClear
Clears CRC fail interrupt
• Bit 3 – RxFecFail_IntClear
Clears FEC fail interrupt
• Bit 2 – RxPktHeaderRdy_IntClear
Clears RX packet header arrival interrupt
• Bit 1 – RxPayHeaderRdy_IntClear
Clears RX payload header arrival interrupt
• Bit 0 – RxPayloadRdy_IntClear
Clears RX payload completion interrupt
All events related to packet RX/TX as well as events generated by compare timers can acti-
vate the “Bluetooth Baseband” system interrupt. Conditions related to Bluetooth Baseband
FIFOs can activate “Bluetooth Baseband FIFOs” system interrupt.
Each event related to packet RX/TX, or generated by a compare timer, is always latched on
the corresponding bit of IntStatus register. The bit is set when the event occurs. The bit is
reset when the corresponding bit of IntClear register is set by the firmware to acknowledge the
event.
However, an event related to packet RX/TX or generated by a compare timer will produce an
interrupt only if the corresponding bit of IntMask register has been set by firmware.
Conditions related to Bluetooth Baseband FIFOs are “TX FIFO almost full” and “RX FIFO
almost empty”. These conditions are not latched, but just reflected on the corresponding bits of
IntStatus register. Bluetooth Baseband FIFO conditions have no corresponding bits in IntClear
register, because they will be automatically reset after proper FIFO service by firmware.
Bluetooth Baseband FIFO conditions will produce an interrupt only if the corresponding bit of
IntMask register has been set by firmware.
RxFifoCtrlStatus
addr: 600060 hex R/W 32 bits
• Bits 31..15 – Reserved
• Bit 14 R – Empty
Set by hardware while FIFO is empty
• Bit 13 R Full – Set by hardware while FIFO is full
• Bit 12 W – Reset
Set by firmware to discard any possible FIFO contents. Auto-clear.
• Bits 11..6 R/W – Threshold[5...0]
Set by firmware to define the minimum level at which FIFO is considered “almost full”
• Bits 5..0 R – Level[5...0]
Current FIFO level, i.e. number of received bytes into FIFO waiting to be read
Note: Default Value: 00000000 hex
RxFifoReadPort
addr: 600064 hex R 32 bits