Owner manual

40
AT76C551
1612D–08/01
• Bits 23..0 – 3wb_, Data[23:0]
24-bit data word to be send on the 3-wire bus. MSB is sent first.
Note: Default Value: 00000000 hex
IntStatus
addr: 600054 hex R 32 bits
• Bits 31..13 – Reserved
• Bit 12 – TxFifoAlmEmpty_IntStatus
TX FIFO almost empty interrupt status.
• Bit 11 – RxFifoAlmFull_IntStatus
RX FIFO almost full interrupt.
• Bit 10 – GenPurpTim_ IntStatus
General purpose compare timer interrupt.
• Bit 9 – TxAcCodeComplete_IntStatus
RX/TX start compare timer interrupt enable.
• Bit 8 – RxTxStart_ IntStatus
RX/TX start compare timer interrupt.
• Bit 7 – TxPktComplete_IntStatus
TX packet completion interrupt.
• Bit 6 – RxCorrelTrig_ IntStatus
Correlator trigger interrupt.
• Bit 5 – RxHecFail_IntStatus
HEC fail interrupt.
• Bit 4 – RxCrcFail_ IntStatus
CRC fail interrupt.
• Bit 3 – RxFecFail_ IntStatus
FEC fail interrupt.
• Bit 2 – RxPktHeaderRdy_IntStatus
RX packet header arrival interrupt.
• Bit 1 – RxPayHeaderRdy_IntStatus
RX payload header arrival interrupt.
• Bit 0 – RxPayloadRdy_IntStatus
RX payload completion interrupt.
Note: Default Value: 00000000 hex
IntMask
addr: 600058 hex R/W 32 bits
• Bits 31..13 – Reserved
• Bit 12 – TxFifoAlmEmpty_IntEnable
TX FIFO almost empty interrupt enable.