Owner manual

37
AT76C551
1612D–08/01
CLKCtrl
addr: 600038 hex R/W 32 bits
• Bits 31..4 – Reserved
• Bit 3 – cmpCLKN0_invert
0: Native clock bit 0 is not inverted for timer comparisons.
1: Native clock bit 0 is inverted for timer comparisons.
Bit 3 value is “don’t care” if bit 0 of the register is reset.
• Bit 2 – ForcePhase_, Adjust
Set by firmware to force native clock phase adjustment, i.e. set native clock phase equal to
CLKPhaseCorrelCorrect register contents. Auto-clear.
• Bit 1 – AutoPhaseAdjust
0: Native clock phase is not auto-adjusted.
1: Native clock phase is auto-adjusted, i.e. set equal to CLKPhaseCorrelCorrect register con-
tents just after each correlator trigger.
• Bit 0 – cmpCLKN0_ enable
0: Compare timer event is generated when compare timer bits 14 - 0 are equal to native clock
phase.
1: Compare timer event is generated when compare timer bits 14 - 0 are equal to native clock
phase AND compare timer bit 15 is equal to native clock bit 0 (possibly inverted).
Note: Default Value: 00000000 hex
CmpTimer_RxTxStart
addr: 60003C hex R/W 32 bits
• Bits 15..0 – CmpTimer_, RxTxStart[15:0]
Sets compare timer for packet RX or TX procedure start
Note: Default Value: 00000000 hex
CmpTimer_GenPurpose
addr: 600040 hex R/W 32 bits
• Bits 15..0 – CmpTimer_, GenPurpose[15:0]
Sets general purpose compare timer
Note: Default Value: 00000000 hex
Compare timers are used to notify an event during a full-slot or a half-slot. Each compare timer
is compared to current native clock phase. Optionally, MSB of each compare timer can be
compared to bit 0 of native clock (possibly inverted).
When compare timer matches current native clock phase and current native clock bit 0, the
corresponding event is generated.
CmpTimer_RxTxStart generates a maskable interrupt and starts RX or TX procedure, if the
corresponding bit of TcCommand register has been set.
CmpTimer_GenPurpose only generates a maskable interrupt.