Owner manual

36
AT76C551
1612D–08/01
• Bits 27..0 – CLKN[27:0]
Provides native clock current value to firmware.
Note: Default Value: 00000000 hex
CLOCK
addr: 600024 hex R/W 32 bits
• Bits 31..28 – Reserved
• Bits 27..0 – CLOCK[27:0]
In this register specific fields of device’s native clock or of transmitter’s estimated in receiver
native clock are set.
Note: Default Value: 00000000 hex
CLKPhase
addr: 600028 hex R/W 32 bits
• Bits 31..15 – Reserved
• Bits 14..0 – CLKPhase[14:0]
Provides native clock phase current value to firmware. Native clock phase is estimated in sys-
tem clock cycles.
Note: Default Value: 00000000 hex
CLKPhaseCorrelCorrect
addr: 60002C hex R/W 32 bits
• Bits 31..15 – Reserved
• Bits 14..0 CLKPhase_, Correl_, Correct[14:0]
Provides slave’s hardware with the proper native clock phase value just after correlator trigger.
At this moment slave’s hardware automatically adjusts CLKN with CLKN of corresponding
master.
Note: Default Value: 00000000 hex
CLKPhaseLimit
addr: 600030 hex R/W 32 bits
• Bits 31..15 – Reserved
• Bits 14..0 – CLKPhase_, Limit[14:0]
Sets native clock phase maximum value in system clock cycles. Effectively sets half-slot dura-
tion in system clock cycles.
Note: Default Value: 00000000 hex
CLKPhaseWhenCorrel
addr: 600034 hex R/W 32 bits
• Bits 31..15 – Reserved
• Bits 14..0 – CLKPhase_, When_, Correl[14:0]
Samples and holds native clock phase at correlator trigger. Thus enables slave-to-master
clock drift estimation.
Note: Default Value: 00000000 hex