Owner manual

13
AT76C551
1612D–08/01
ASYNC O Frame Sync – Out
ACLK_IN I Master Clock – In
ABCLK_IN I Bit Clock – In
ASYNC_IN I Frame Sync – In
JTAG Pins
DB_DATA O Debug data port
DB_CLK O Debug clock port
NTRST I JTAG reset input
TCK I JATG clock
TDI I JTAG data input
TDO I JTAG data output
TMS I JTAG master select input
TEST Pins
TEST_CTRL I For production test
TEST_ECK I For production test
PLL_TEST_PIN I For production test.
Signal Description – Pin Name Order (Continued)
I = Input, O = Output, B = Bidirectional, Analog I = Analog Input, Analog O = Analog Output
Pin Name
Type
Description