Manual

AT75C310
42
Note: 1. Bit number refers to the data bit which corresponds to this signal in each of the User Interface registers.
Note: 1. Bit number refers to the data bit which corresponds to this signal in each of the User Interface registers.
Table 13. PIO Controller A Connection Table
PIO Controller A Peripheral
Reset State
Pin
Number
Bit
Number
(1)
Port Name Port Name Signal Description Signal Direction
0 PA0 OAKAIN0
OakDSPCore A User Input Input
PIO 71
1 PA1 OAKAIN1
OakDSPCore A User Input Input
PIO 72
2PA2OAKAOUT0
OakDSPCore A User Output Output
PIO 73
3PA3OAKAOUT1
OakDSPCore A User Output Output
PIO 74
4 PA4 OAKBIN0
OakDSPCore B User Input Input
PIO 77
5 PA5 OAKBIN1
OakDSPCore B User Input Input
PIO 78
6 PA6 OAKBOUT0
OakDSPCore B User Output Output
PIO 79
7 PA7 OAKBOUT1
OakDSPCore B User Output Output
PIO 80
8PA8TCLK0
Timer 0 External Clock Input
PIO 82
9PA9TIOA0
Timer 0 Signal A Input/Output
PIO 83
10 PA10 TIOB0
Timer 0 Signal B Input/Output
PIO 85
11 PA11 SCLKA
Serial Clock Input/Output
PIO 86
12 PA12 NPCS1
Optional SPI Chip Select 1 Output
PIO 88
Table 14. PIO Controller B Connection Table
PIO Controller B Peripheral
Reset State
Pin
Number
Bit
Number
(1)
Port Name Port Name Signal Description Signal Direction
0 PB0 TCLK1 Timer 1 External Clock Input PIO 55
1 PB1 TIOA1 Timer 1 Signal A Input/Output PIO 53
2 PB2 TIOB1 Timer 1 Signal B Input/Output PIO 51
3PB3 –– –PIO 47
4PB4 –– –PIO 44
5 PB5 NRIA Ring Indicator Input PIO 43
6 PB6 NWDOVF Watchdog Overflow Output PIO 42
7 PB7 NCE1 Chip Select Output PIO 38
8 PB8 NCE2 Chip Select Output PIO 54
9PB9 –– –PIO 52