Manual

AT75C310
116
• SCBR: Serial Clock Baud Rate
In master mode, the SPI interface uses a modulus counter to derive the SPCK baud rate from the SPI master clock
(selected between ACLK and ACLK/32). The baud rate is selected by writing a value from 2 to 255 in the field SCBR.
The following equation determines the SPCK baud rate:
Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state
value. No serial transfers may occur. At reset, baud rate is disabled.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equation determines the delay:
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip
select. The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, a delay of four SPI master clock periods is inserted.
Otherwise, the following equation determines the delay:
1101 Reserved
1110 Reserved
1111 Reserved
BITS[3:0] Bits per Transfer
SPCK_Baud_Rate
SPI_Master_Clock_Frequency
2SCBR
×
---------------------------------------------------------------------------------=
NPCS_to_SPCK_Delay DLYBS SPI_Master_Clock_Period
×=
Delay_after_Transfer 32 DLYBCT
× SPI_Master_Clock_Period×=