Manual

AT75C310
108
SPI Control Register
Register Name: SP_CR
Access Type: Write-only
• SPIEN: SPI Enable
0 = No effect.
1 = Enables the SPI to transfer and receive data.
• SPIDIS: SPI Disable
0 = No effect.
1 = Disables the SPI.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
• SWRST: SPI Software reset
0 = No effect.
1 = Resets the SPI.
A software-triggered hardware reset of the SPI interface is performed.
0x1C
Interrupt Mask Register
SP_IMR Read-only 0
0x20
Reserved
–––
0x24
Reserved
–––
0x28
Reserved
–––
0x2C
Reserved
–––
0x30
Chip Select Register 0
SP_CSR0 Read/write 0
0x34
Chip Select Register 1
SP_CSR1 Read/write 0
0x38
Reserved
–––
0x3C
Reserved
–––
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST –––––SPIDIS SPIEN
Table 21. SPI Memory Map (Continued)
Offset Register Description Register Name Access Reset State