User Manual

18
AT45DB642
1638F–DFLSH–09/02
Reset Timing (Inactive Clock Polarity Low Shown)
Note: The CS signal should be in the high state before the RESET signal is deasserted.
Serial/Parallel Interface Timing
Command Sequence for Read/Write Operations (Except Status Register Read)
CS
SCK/CLK
RESET
SO or I/O7 - I/O0
(OUTPUT)
HIGH IMPEDANCE HIGH IMPEDANCE
SI or I/O7 - I/O0
(INPUT)
tRST
tREC tCSS
CS
SER/PAR
t
SPH
t
SPS
SI or I/O7 - I/O0
(INPUT)
CMD 8 bits
8 bits
8 bits
MSB
Page Address
(PA12 - PA0)
Byte/Buffer Address
(BA10 - BA0/BFA10 - BFA0)
LSBX X X X X X X X X X X X X X X X
X X X X X X X X