Instruction Manual

38
3597J–DFLASH–4/08
AT45DB321D
21.6 Reset Timing
Note: The CS signal should be in the high state before the RESET signal is deasserted.
21.7 Command Sequence for Read/Write Operations for Page Size 512 Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
21.8 Command Sequence for Read/Write Operations for Page Size 528 Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
CS
SCK
RESET
SO (OUTPUT)
HIGH IMPEDANCE HIGH IMPEDANCE
SI (INPUT)
t
RST
t
REC
t
CSS
SI (INPUT) CMD 8 bits
8 bits
8 bits
Page Address
(A21 - A9)
X X X X X X X X X X X X X X X X LSB
X X X X X X X X
Byte/Buffer Address
(A8 - A0/BFA8 - BFA0)
MSB
Don’t Care
Bits
Page Address
(PA12 - PA0)
Byte/Buffer Address
(BA9 - BA0/BFA9 - BFA0)
SI (INPUT)
CMD 8 bits
8 bits
8 bits
X X X XX X X X X X X X LSB
X X X X X X X X
MSB
1 Don’t Care
Bit
X X X X