User Manual

9
AT45DB161B
2224E–DFLSH–10/02
WRITE PROTECT: If the WP pin is held low, the first 256 p ages of t he main m emory
cannot be r eprog ra mme d. The only way to rep ro gram the fir s t 256 pa ges is to fir st dr iv e
the protec t pin high and then us e the program comm ands previo usly mentioned . The
WP
pin is internal ly pulle d high; th erefore , connec tion of the WP pin is not necessary if
this pin and fea ture wi ll not be u tiliz ed. Howe ver, it is recomme nded th at th e WP
pin be
driven high externally whenever possible.
RESET: A low state on the reset pin (RESET) will terminate the operation in progress
and res et the in terna l state machi ne to a n idle state. T he de vice will re main i n the r eset
condition as long as a low level is present on the RESET
pin. Normal operation can
resume once the RESET
pin is brought back to a high level.
The device incorporates an inte rnal power-on reset circuit, so there are no restrictions
on the RESE T pin during power-on sequences. The RESET pin is also in ternal ly pulle d
high; ther efo re, conne ction of th e RE SE T
pin is not n ec es sa ry if thi s pin and feature will
not be utilized. However, it is rec ommended that the RESET
pin be driven high exter-
nally whenever possible.
READY/BUSY: This open drain outp ut pin w ill be driven low when the dev ice is b usy in
an internally self-timed operation. This pin, which is normally in a high state (through
a1k
W external pull-up resistor), will be pulled low during programming operations, com-
pare operations, and during page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the
device will d efault to SPI Mode 3. In add ition, th e SO p in will be in a h igh-impeda nce
state, an d a high- to-low tr ansition on the CS
pin will be required to start a valid instruc-
tion. The SPI mode will be automatically selected on every falling edge of CS
by
sampling the inactive clock state.