User Manual

4
AT45DB161B
2224E–DFLSH–10/02
cycle, al lowing one con tinuous read ope ration without th e nee d of additional addr ess
sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked
into the device followed by 24 address bits and 32 don’t care bits. The first two bits of
the 24-bit address sequence are reserved for upward and downward compatibility to
larger and smaller density devices (see Notes under “Command Sequence for
Read/Wri te Operations ” d ia gram) . The next 12 addre ss bi ts (P A11 - PA 0) spec if y which
page of the main memory array to read, and the last ten bits (BA9 - BA0) of the 24-bit
address sequence specify the starting byte address within the page. The 32 don’t care
bits tha t fo ll ow t he 24 addres s bi ts ar e nee ded to initializ e t he r e ad operation. Fol lo wing
the 32 don’t care bits, additional clock pulses on the SCK pin will result in serial data
being output on the SO (serial output) pin.
The CS
pin must remain low during the loading of the opcode, the address bits, the don’t
care bits , and the re ading of da ta. When th e end of a page in main mem ory is reac hed
during a Continuous Array Read, the device will continue reading at the beginning of the
next page with no delays incurred during the page boundary crossover (the crossover
from the end of on e page to the begi nning of the n ext page). When th e last bit in th e
main memory array has been read, the device will continue reading back at the begin-
ning of the first pag e of memory. A s with crossing ov er page bound aries, no dela ys will
be incurred when wrapping around from the end of the array to the beginning of the
array.
A low-to -high tran sition o n the CS
pin will term inate the read operation and tri-sta te the
SO pin. The maximum SCK frequency allowable for the Continuous Array Read is
defined by the f
CAR
specifi cation . The Contin uous Arr ay Read bypas ses both da ta buff-
ers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data
directly from any one of the 4096 pages in the main memory, bypassing both of the data
buffers and leaving the contents of the buffers unchanged. To start a page read, an
opcode of 52H or D2 H m us t b e cl ocked into th e d evic e fol low ed by 24 a ddres s bi ts an d
32 don’t care bits. The first two bits of the 24-bit address sequence are reserved bits, the
next 12 address bits (PA11 - PA0) specify the page address, and the next ten address
bits (BA9 - BA0) specify the starting byte address within the page. The 32 don’t care bits
which follow the 24 address bits are sent to initialize the read operation. Following the
32 don’t c ar e bits, additional pul s es on S CK r esul t in ser i al d ata b ein g ou tput on the SO
(serial output) pin. The CS
pin mus t remain low during the loading of the opc ode, the
address bits, the don’t care bits, and the reading of data. When the end of a page in
main memory is reached during a Main Memory Page Read, the device will continue
reading at the beginning of the s ame page. A low-to- high transition on the CS
pin will
terminate the read operation and tri-state the SO pin.
BUFFER READ: Data ca n be read from e ither one of the two buffers , usin g differen t
opcodes to s pecif y whi ch bu ffer t o rea d fr o m. A n opc od e o f 5 4H o r D4H is u se d t o r ea d
data from bu ffer 1 , an d a n o pco de of 5 6H o r D6H is used to re ad data fr om buf fer 2. To
perform a Buffer Read, the eight bits of the opcode must be followed by 14 don’t care
bits, ten address bits, and eight don’t care bits. Since the buffer si ze is 528 bytes, ten
addres s bits (B F A9 - BFA0 ) are r eq ui red to spec if y t he first by te of d ata to be r e ad f ro m
the buffer. The CS
pin must remain low during the loading of the opcode, the address
bits, the don’t care bits, and the reading of data. When the end of a buffer is reached,
the device will continue reading back at the beginning of the buffer. A low-to-high transi-
tion on the CS
pin will terminate the read operation and tri-state the SO pin.
STATUS REGISTER READ: Th e sta tus regi ster c an b e us ed to deter mine th e dev ice ’s
Ready/B usy statu s, the re sult of a Ma in Memor y Page to Buffer Compa re opera tion, or
the device density. To read the status register, an opcode of 57H or D7H must be