User guide
Table Of Contents
- Features
- 1. Description
- 2. Pin Configurations and Pinouts
- 3. Block Diagram
- 4. Memory Array
- 5. Device Operation
- 6. Read Commands
- 7. Program and Erase Commands
- 8. Sector Protection
- 9. Hardware Controlled Protection
- 10. Security Features
- 11. Additional Commands
- 12. Deep Power-down
- 13. “Power of 2” Binary Page Size Option
- 14. Manufacturer and Device ID Read
- 15. Command Tables
- 16. Power-on/Reset State
- 17. System Considerations
- 18. Electrical Specifications
- 19. Input Test Waveforms and Measurement Levels
- 20. Output Test Load
- 21. AC Waveforms
- 21.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66MHz)
- 21.2 Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66MHz)
- 21.3 Waveform 3 – RapidS Mode 0 (FMAX = 66MHz)
- 21.4 Waveform 4 – RapidS Mode 3 (FMAX = 66MHz)
- 21.5 Utilizing the RapidS Function
- 21.6 Reset Timing
- 21.7 Command Sequence for Read/Write Operations for Page Size 256-Bytes (Except Status Register Read, Manufacturer and Device ID Read)
- 21.8 Command Sequence for Read/Write Operations for Page Size 264-Bytes (Except Status Register Read, Manufacturer and Device ID Read)
- 22. Write Operations
- 23. Read Operations
- 24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 3
- 24.1 Continuous Array Read (Legacy Opcode E8H)
- 24.2 Continuous Array Read (Opcode 0BH)
- 24.3 Continuous Array Read (Low Frequency: Opcode 03H)
- 24.4 Main Memory Page Read (Opcode: D2H)
- 24.5 Buffer Read (Opcode D4H or D6H)
- 24.6 Buffer Read (Low Frequency: Opcode D1H or D3H)
- 24.7 Read Sector Protection Register (Opcode 32H)
- 24.8 Read Sector Lockdown Register (Opcode 35H)
- 24.9 Read Security Register (Opcode 77H)
- 24.10 Status Register Read (Opcode D7H)
- 24.11 Manufacturer and Device Read (Opcode 9FH)
- 25. Auto Page Rewrite Flowchart
- 26. Ordering Information
- 27. Packaging Information
- 28. Revision History
- 29. Errata

33
3596N–DFLASH–11/2012
AT45DB081D
Notes: 1. I
CC1
during a buffer read is 20mA maximum @ 20MHz
2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design to be 5V tolerant
Table 18-3. DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
DP
Deep Power-down Current
CS, RESET, WP = V
IH
,all
inputs at CMOS levels
15 25 µA
I
SB
Standby Current
CS, RESET, WP = V
IH
,all
inputs at CMOS levels
25 50 µA
I
CC1
(1)
Active Current, Read Operation
f = 20MHz; I
OUT
= 0mA;
V
CC
= 3.6V
710mA
f = 33MHz; I
OUT
= 0mA;
V
CC
= 3.6V
812mA
f = 50MHz; I
OUT
= 0mA;
V
CC
= 3.6V
10 14 mA
f = 66MHz; I
OUT
= 0mA;
V
CC
= 3.6V
11 15 mA
I
CC2
Active Current, Program/Erase
Operation
V
CC
= 3.6V 12 17 mA
I
LI
Input Load Current V
IN
= CMOS levels 1 µA
I
LO
Output Leakage Current V
I/O
= CMOS levels 1 µA
V
IL
Input Low Voltage V
CC
x 0.3 V
V
IH
Input High Voltage V
CC
x 0.7 V
V
OL
Output Low Voltage I
OL
= 1.6mA; V
CC
= 2.7V 0.4 V
V
OH
Output High Voltage I
OH
= -100µA V
CC
-0.2V V










