Instruction Manual

9
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Figure 5. The Cell
OUT OUT
RESET/SET
CLOCK
FB
X = Diagonal Direct Connect or Bus
Y = Orthogonal Direct Connect or Bus
W = Bus Connection
Z = Bus Connection
FB = Internal Feedback
10
Z
D
Q
"1" NW NE SE SW
"1"
"1"
"1""0"
XWY
XZWY
"1" N E S W
8X1 LUT 8X1 LUT
X
Y
NW NE SE SW N E S W
V1
H1
V2
H2
V3
H3
V4
H4
V5
H5
"1" OE
H
OE
V
L
Pass gates