Instruction Manual

36
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Notes: 1. CMOS buffer delays are measured from a V
IH
of 1/2 V
CC
at the pad to the internal V
IH
at A. The input buffer load is constant.
2. Buffer delay is to a pad voltage of 1.5V with one output switching.
3. Parameter based on characterization and simulation; not tested in production.
4. Exact power calculation is available in Atmel FPGA Designer software.
AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
CC
= 3.0V, temperature = 70°C
Minimum times based on best case: V
CC
= 3.6V, temperature = 0° C
Cell Function Parameter Path -3 Units Notes
Async RAM
Write t
WECYC
(Minimum) cycle time 12.0 ns
Write t
WEL
(Minimum) we 5.0 ns Pulse width low
Write t
WEH
(Minimum) we 5.0 ns Pulse width high
Write t
AWS
(Minimum) wr addr setup -> we 5.3 ns
Write t
AWH
(Minimum) wr addr hold -> we 0.0 ns
Write t
DS
(Minimum) din setup -> we 5.0 ns
Write t
DH
(Minimum) din hold -> we 0.0 ns
Write/Read t
DD
(Maximum) din -> dout 8.7 ns rd addr = wr addr
Read t
AD
(Maximum) rd addr -> dout 6.3 ns
Read t
OZX
(Maximum) oe -> dout 2.9 ns
Read t
OXZ
(Maximum) oe -> dout 3.5 ns
Sync RAM
Write t
CYC
(Minimum) cycle time 12.0 ns
Write t
CLKL
(Minimum) clk 5.0 ns Pulse width low
Write t
CLKH
(Minimum) clk 5.0 ns Pulse width high
Write t
WCS
(Minimum) we setup -> clk 3.2 ns
Write t
WCH
(Minimum) we hold -> clk 0.0 ns
Write t
ACS
(Minimum) wr addr setup -> clk 5.0 ns
Write t
ACH
(Minimum) wr addr hold -> clk 0.0 ns
Write t
DCS
(Minimum) wr data setup -> clk 3.9 ns
Write t
DCH
(Minimum) wr data hold -> clk 0.0 ns
Write/Read t
CD
(Maximum) clk -> dout 5.8 ns rd addr = wr addr
Read t
AD
(Maximum) rd addr -> dout 6.3 ns
Read t
OZX
(Maximum) oe -> dout 2.9 ns
Read t
OXZ
(Maximum) oe -> dout 3.5 ns